From: Oliver Upton <oliver.upton@linux.dev>
To: Marc Zyngier <maz@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev,
kvm@vger.kernel.org, James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Ricardo Koller <ricarkol@google.com>,
Reiji Watanabe <reijiw@google.com>
Subject: Re: [PATCH v2 01/14] arm64: Add ID_DFR0_EL1.PerfMon values for PMUv3p7 and IMP_DEF
Date: Fri, 4 Nov 2022 20:47:20 +0000 [thread overview]
Message-ID: <Y2V6WIu40Cg2ShXV@google.com> (raw)
In-Reply-To: <20221028105402.2030192-2-maz@kernel.org>
On Fri, Oct 28, 2022 at 11:53:49AM +0100, Marc Zyngier wrote:
> Align the ID_DFR0_EL1.PerfMon values with ID_AA64DFR0_EL1.PMUver.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
FYI, another pile of ID reg changes is on the way that'll move DFR0 to a
generated definition.
https://lore.kernel.org/linux-arm-kernel/20220930140211.3215348-1-james.morse@arm.com/
--
Thanks,
Oliver
> ---
> arch/arm64/include/asm/sysreg.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 7d301700d1a9..84f59ce1dc6d 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -698,6 +698,8 @@
> #define ID_DFR0_PERFMON_8_1 0x4
> #define ID_DFR0_PERFMON_8_4 0x5
> #define ID_DFR0_PERFMON_8_5 0x6
> +#define ID_DFR0_PERFMON_8_7 0x7
> +#define ID_DFR0_PERFMON_IMP_DEF 0xf
>
> #define ID_ISAR4_SWP_FRAC_SHIFT 28
> #define ID_ISAR4_PSR_M_SHIFT 24
> --
> 2.34.1
>
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next prev parent reply other threads:[~2022-11-04 20:48 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-28 10:53 [PATCH v2 00/14] KVM: arm64: PMU: Fixing chained events, and PMUv3p5 support Marc Zyngier
2022-10-28 10:53 ` [PATCH v2 01/14] arm64: Add ID_DFR0_EL1.PerfMon values for PMUv3p7 and IMP_DEF Marc Zyngier
2022-11-04 20:47 ` Oliver Upton [this message]
2022-11-05 9:42 ` Marc Zyngier
2022-10-28 10:53 ` [PATCH v2 02/14] KVM: arm64: PMU: Align chained counter implementation with architecture pseudocode Marc Zyngier
2022-10-28 10:53 ` [PATCH v2 03/14] KVM: arm64: PMU: Always advertise the CHAIN event Marc Zyngier
2022-11-12 8:01 ` Reiji Watanabe
2022-10-28 10:53 ` [PATCH v2 04/14] KVM: arm64: PMU: Distinguish between 64bit counter and 64bit overflow Marc Zyngier
2022-10-28 10:53 ` [PATCH v2 05/14] KVM: arm64: PMU: Narrow the overflow checking when required Marc Zyngier
2022-10-28 10:53 ` [PATCH v2 06/14] KVM: arm64: PMU: Only narrow counters that are not 64bit wide Marc Zyngier
2022-10-28 10:53 ` [PATCH v2 07/14] KVM: arm64: PMU: Add counter_index_to_*reg() helpers Marc Zyngier
2022-10-28 10:53 ` [PATCH v2 08/14] KVM: arm64: PMU: Simplify setting a counter to a specific value Marc Zyngier
2022-10-28 10:53 ` [PATCH v2 09/14] KVM: arm64: PMU: Do not let AArch32 change the counters' top 32 bits Marc Zyngier
2022-10-28 10:53 ` [PATCH v2 10/14] KVM: arm64: PMU: Move the ID_AA64DFR0_EL1.PMUver limit to VM creation Marc Zyngier
2022-11-03 4:55 ` Reiji Watanabe
2022-11-03 8:44 ` Marc Zyngier
2022-11-03 14:52 ` Reiji Watanabe
2022-10-28 10:53 ` [PATCH v2 11/14] KVM: arm64: PMU: Allow ID_AA64DFR0_EL1.PMUver to be set from userspace Marc Zyngier
2022-11-03 5:31 ` Reiji Watanabe
2022-11-03 10:24 ` Marc Zyngier
2022-11-04 7:00 ` Reiji Watanabe
2022-11-04 12:20 ` Marc Zyngier
2022-11-04 15:53 ` Reiji Watanabe
2022-11-06 12:47 ` Marc Zyngier
2022-11-08 5:36 ` Reiji Watanabe
2022-11-13 10:56 ` Marc Zyngier
2022-10-28 10:54 ` [PATCH v2 12/14] KVM: arm64: PMU: Allow ID_DFR0_EL1.PerfMon " Marc Zyngier
2022-10-28 10:54 ` [PATCH v2 13/14] KVM: arm64: PMU: Implement PMUv3p5 long counter support Marc Zyngier
2022-10-28 10:54 ` [PATCH v2 14/14] KVM: arm64: PMU: Allow PMUv3p5 to be exposed to the guest Marc Zyngier
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