From: Catalin Marinas <catalin.marinas@arm.com>
To: richard clark <richard.xnu.clark@gmail.com>
Cc: mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org
Subject: Re: LDREX and STREX in heterogeneous system？
Date: Wed, 9 Nov 2022 09:25:59 +0000 [thread overview]
Message-ID: <Y2tyJ7F5umVKZ9NF@arm.com> (raw)
In-Reply-To: <CAJNi4rOVB8ud+fobf0k3jnv2v2U+nk49oUha6DpKNtA9bOX43A@mail.gmail.com>
On Wed, Nov 09, 2022 at 04:34:13PM +0800, richard clark wrote:
> Suppose in a heterogeneous system, there're cortex-M7 and cortex-A72
> sharing the same bus. Does the below code sequence work as (ldr/str)ex
> expected?
>
> r2 point to a uncached shared memory between M7 and A72
>
> M7 A72
> ldrex r1, [r2]
> -------------------------> strex r0, r1, [r2]
In general, it won't. The exclusives are supposed to work in the same
inner shareable domain, so it depends on how the SoC has the M7 and A72
wired up. Are they cache coherent with each-other? Is there a global
exclusive monitor? The M7 may also need the MPU regions set up with the
Shareable attribute.
--
Catalin
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next prev parent reply other threads:[~2022-11-09 9:27 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-09 8:34 LDREX and STREX in heterogeneous system？ richard clark
2022-11-09 9:25 ` Catalin Marinas [this message]
2022-11-10 3:27 ` richard clark
2022-11-11 22:40 ` Catalin Marinas
2022-11-17 1:32 ` richard clark
2022-11-17 14:06 ` Catalin Marinas
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