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[2003:e4:1f20:1d00:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id y14-20020aa7ccce000000b0045b4b67156fsm6001694edt.45.2022.11.15.02.25.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Nov 2022 02:25:14 -0800 (PST) Date: Tue, 15 Nov 2022 11:25:12 +0100 From: Thierry Reding To: Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= Cc: Andre Przywara , Chen-Yu Tsai , Samuel Holland , Jernej Skrabec , Rob Herring , Krzysztof Kozlowski , =?utf-8?B?Q2zDqW1lbnQgUMOpcm9u?= , Icenowy Zheng , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-pwm@vger.kernel.org Subject: Re: [PATCH v2 02/10] ARM: dts: suniv: f1c100s: add PWM node Message-ID: References: <20221107005433.11079-1-andre.przywara@arm.com> <20221107005433.11079-3-andre.przywara@arm.com> <20221115101926.dldj6ralahdzhj7k@pengutronix.de> MIME-Version: 1.0 In-Reply-To: <20221115101926.dldj6ralahdzhj7k@pengutronix.de> User-Agent: Mutt/2.2.8 (2022-11-05) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221115_022520_166144_24FE9480 X-CRM114-Status: GOOD ( 19.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============4998060534503703399==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============4998060534503703399== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="l6W4QUPthCHqA1lj" Content-Disposition: inline --l6W4QUPthCHqA1lj Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Nov 15, 2022 at 11:19:26AM +0100, Uwe Kleine-K=C3=B6nig wrote: > On Mon, Nov 07, 2022 at 12:54:25AM +0000, Andre Przywara wrote: > > The Allwinner F1C100s family of SoCs contain a PWM controller compatible > > to the one used in the A20 chip. > > Add the DT node so that any users can simply enable it in their board > > DT. > >=20 > > Signed-off-by: Andre Przywara >=20 > I checked "by hand" that this matches the modified binding in patch > 01/10.=20 >=20 > Reviewed-by: Uwe Kleine-K=C3=B6nig >=20 > I assume the whole series will go in via a tree different from the PWM > tree? While this is Thierry's area of maintenance, I'd be surprised if > he had concerns about that. Yeah, it's probably best for the Allwinner maintainers to pick this up into their tree so that the bindings changes go along with the DT changes. Acked-by: Thierry Reding --l6W4QUPthCHqA1lj Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmNzaQgACgkQ3SOs138+ s6Fn9RAAt+XRPFAS9efnEeAg7yzhd5KACfgZ5iOHVCTYLLgA67VmqUZ/LS/fjb/t 0pbACyLypmoGflQL5YjV5jwg1smW6ubWWCw9BJq8VlZ0eISjx3QkRxZSaK1P5Kil N/GyeLV53ezyV8gBE0vMBDKPn7XSH0KpJbs8ompGb36jWBAwT4r7E8Ze+MBDTUtP HcQZbrVNCReYBIo38G6Nav+2lZnYHyb2rey2WMuGoWl38WR+68/V/Fo+2kRB14hV FpRNE/QCRNa7e1W7JgbjUTrDTt/NrOPV2tnMDUofpecSUeRMGMG3vF87pQLMm92Y Hw6lYMRBTR3cab0waBUSXJCBOIefdPsEgOxkQ8ap3phdsvrsgLLy/DxWtyR6GNyE s0SjbCnutGVmVXfLUMUH8Z3MPPr5TKw8cjsRIzKgCxBkNcpyu9Me2SD6Npmf379/ 4gyGw9g/3eS3UtQc9HmiBgpyuhsNljCEVvoG6+TMbSMtBKttiKKiwpvJuMz81caF g0QmqGGWNitbZJspwhqGFLFckFDQ+xkmX20vFA3NPE6eMtkOivfaslYZVdJRGmZM HDYAFfTbXGEIawHftmIrrm8VNZfs/CToSxayQecZGjVPlyMEBxyZXbxJC3S5ZTuc dcMif7pTYY2Jk/OEikFG8G38H2IeQGHEee1+YRXv46oSx1pyh+I= =TpgC -----END PGP SIGNATURE----- --l6W4QUPthCHqA1lj-- --===============4998060534503703399== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============4998060534503703399==--