From: Catalin Marinas <catalin.marinas@arm.com>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, will@kernel.org,
Suzuki K Poulose <suzuki.poulose@arm.com>,
James Morse <james.morse@arm.com>,
Jonathan Corbet <corbet@lwn.net>,
Mark Rutland <mark.rutland@arm.com>,
linux-doc@vger.kernel.org
Subject: Re: [PATCH V2 2/2] arm64: errata: Workaround possible Cortex-A715 [ESR|FAR]_ELx corruption
Date: Wed, 16 Nov 2022 09:00:12 +0000 [thread overview]
Message-ID: <Y3SmnJLO92zc20lD@arm.com> (raw)
In-Reply-To: <438ddc78-ded6-d464-f917-6b8749626f16@arm.com>
On Wed, Nov 16, 2022 at 10:12:34AM +0530, Anshuman Khandual wrote:
> Planning to apply the following change after this patch.
>
> diff --git a/arch/arm64/mm/hugetlbpage.c b/arch/arm64/mm/hugetlbpage.c
> index 6552947ca7fa..cd8d96e1fa1a 100644
> --- a/arch/arm64/mm/hugetlbpage.c
> +++ b/arch/arm64/mm/hugetlbpage.c
> @@ -562,14 +562,14 @@ bool __init arch_hugetlb_valid_size(unsigned long size)
>
> pte_t huge_ptep_modify_prot_start(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
> {
> - if (IS_ENABLED(CONFIG_ARM64_WORKAROUND_2645198)) {
> - pte_t pte = READ_ONCE(*ptep);
> + if (IS_ENABLED(CONFIG_ARM64_WORKAROUND_2645198) &&
> + cpus_have_const_cap(ARM64_WORKAROUND_2645198)) {
> /*
> * Break-before-make (BBM) is required for all user space mappings
> * when the permission changes from executable to non-executable
> * in cases where cpu is affected with errata #2645198.
> */
> - if (pte_user_exec(pte) && cpus_have_const_cap(ARM64_WORKAROUND_2645198))
> + if (pte_user_exec(READ_ONCE(*ptep)))
> return huge_ptep_clear_flush(vma, addr, ptep);
> }
> return huge_ptep_get_and_clear(vma->vm_mm, addr, ptep);
> diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
> index c1fb0ce1473c..ec305ea3942c 100644
> --- a/arch/arm64/mm/mmu.c
> +++ b/arch/arm64/mm/mmu.c
> @@ -1705,14 +1705,14 @@ early_initcall(prevent_bootmem_remove_init);
>
> pte_t ptep_modify_prot_start(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
> {
> - if (IS_ENABLED(CONFIG_ARM64_WORKAROUND_2645198)) {
> - pte_t pte = READ_ONCE(*ptep);
> + if (IS_ENABLED(CONFIG_ARM64_WORKAROUND_2645198) &&
> + cpus_have_const_cap(ARM64_WORKAROUND_2645198)) {
> /*
> * Break-before-make (BBM) is required for all user space mappings
> * when the permission changes from executable to non-executable
> * in cases where cpu is affected with errata #2645198.
> */
> - if (pte_user_exec(pte) && cpus_have_const_cap(ARM64_WORKAROUND_2645198))
> + if (pte_user_exec(READ_ONCE(*ptep)))
> return ptep_clear_flush(vma, addr, ptep);
> }
> return ptep_get_and_clear(vma->vm_mm, addr, ptep);
It looks fine to me. Thanks.
--
Catalin
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next prev parent reply other threads:[~2022-11-16 9:05 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-13 1:26 [PATCH V2 0/2] arm64: errata: Workaround Cortex-A715 errata #2645198 Anshuman Khandual
2022-11-13 1:26 ` [PATCH V2 1/2] arm64: Add Cortex-715 CPU part definition Anshuman Khandual
2022-11-15 13:51 ` Catalin Marinas
2022-11-13 1:26 ` [PATCH V2 2/2] arm64: errata: Workaround possible Cortex-A715 [ESR|FAR]_ELx corruption Anshuman Khandual
2022-11-15 13:38 ` Will Deacon
2022-11-15 13:42 ` Will Deacon
2022-11-16 5:49 ` Anshuman Khandual
2022-11-15 14:02 ` Catalin Marinas
2022-11-16 4:42 ` Anshuman Khandual
2022-11-16 9:00 ` Catalin Marinas [this message]
2022-11-16 5:04 ` Anshuman Khandual
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