From: Catalin Marinas <catalin.marinas@arm.com>
To: richard clark <richard.xnu.clark@gmail.com>
Cc: mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org
Subject: Re: LDREX and STREX in heterogeneous system？
Date: Thu, 17 Nov 2022 14:06:18 +0000 [thread overview]
Message-ID: <Y3Y/2uPoggFcwDRN@arm.com> (raw)
In-Reply-To: <CAJNi4rOqt3D9m_wEo-nfRC_wbMvs5W1UtrppTmJwBiiXesfBFg@mail.gmail.com>
On Thu, Nov 17, 2022 at 09:32:50AM +0800, richard clark wrote:
> On Sat, Nov 12, 2022 at 6:40 AM Catalin Marinas <catalin.marinas@arm.com> wrote:
> > On Thu, Nov 10, 2022 at 11:27:23AM +0800, richard clark wrote:
> > > On Wed, Nov 9, 2022 at 5:26 PM Catalin Marinas <catalin.marinas@arm.com> wrote:
> > > > On Wed, Nov 09, 2022 at 04:34:13PM +0800, richard clark wrote:
> > > > > Suppose in a heterogeneous system, there're cortex-M7 and cortex-A72
> > > > > sharing the same bus. Does the below code sequence work as (ldr/str)ex
> > > > > expected?
> > > > >
> > > > > r2 point to a uncached shared memory between M7 and A72
> > > > >
> > > > > M7 A72
> > > > > ldrex r1, [r2]
> > > > > -------------------------> strex r0, r1, [r2]
> > > >
> > > > In general, it won't. The exclusives are supposed to work in the same
> > > > inner shareable domain, so it depends on how the SoC has the M7 and A72
> > > > wired up. Are they cache coherent with each-other? Is there a global
> > > > exclusive monitor? The M7 may also need the MPU regions set up with the
> > > > Shareable attribute.
> > >
> > > Thanks Catalin! AFAIK the M7 and A53 are not in the same Inner
> > > shareable domain: if A53 modifies the SRAM with D$ on, the M7 will
> > > still get the stale data from the same SRAM location. Except that
> > > probably there is not a global exclusive monitor there.
> >
> > An SoC may allow exclusives on a small range of non-cacheable memory but
> > it's not something to infer from the CPUID registers. You'd have to ask
> > the hardware people whether they built a global exclusive monitor and
> > whether that's shared with the M7.
>
> The hardware people confirmed there's no global exclusive monitor in
> the SoC and the M and A are not in the same inner-shareable-domain, so
> order to access the shared resources between M and A in an exclusive
> way, the SoC provides another method as so-called 'hw gate'...
You may want to look at hwspinlock and implement a driver that deals
with this 'hw gate'.
--
Catalin
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prev parent reply other threads:[~2022-11-17 14:07 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-09 8:34 LDREX and STREX in heterogeneous system？ richard clark
2022-11-09 9:25 ` Catalin Marinas
2022-11-10 3:27 ` richard clark
2022-11-11 22:40 ` Catalin Marinas
2022-11-17 1:32 ` richard clark
2022-11-17 14:06 ` Catalin Marinas [this message]
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