From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BE97CC433FE for ; Thu, 17 Nov 2022 14:07:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=rAzRxdOyZQOfbk8tSkhr0Nz2ZC/IcENhD2AzstIj1F4=; b=o8I6MrTz0dvSoz OYQalfx/CNoIxNvuPuvB8TMNiToT09VhvNj5eH8vr7oaUSsU8AZ4AYCWN84R+x+IQ0RnlVI7enZqK V/WeF636kCwsj8YaqiCeEEnSYeY94u7aZjEXp0VCPQyxPIMsUK9jKb09Ry/7MTpvYMza7wr/qtklh RePobta2XTKwJnFFlQC2zxAK2uHEVYFoxShKFc4DHgXCIIZpKDVWZSuOypRwfEPWNxSKx2asq/vrM T/RA2TvaErF4sDDXFg/JKqVCVcAO0fIQVfvqO/uv4EjwfbMXLKGOFwODNMTIKRpYOV5kNYc6xxXov p8mO0KwDb7gDL/ByfNTA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ovfXC-00Eh2E-QG; Thu, 17 Nov 2022 14:06:30 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ovfXA-00Eh0B-AG for linux-arm-kernel@lists.infradead.org; Thu, 17 Nov 2022 14:06:29 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 6481BB81FB4; Thu, 17 Nov 2022 14:06:24 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 31738C433D6; Thu, 17 Nov 2022 14:06:21 +0000 (UTC) Date: Thu, 17 Nov 2022 14:06:18 +0000 From: Catalin Marinas To: richard clark Cc: mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org Subject: Re: LDREX and STREX in =?utf-8?Q?heterogen?= =?utf-8?Q?eous_system=EF=BC=9F?= Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221117_060628_519559_B0D50AC2 X-CRM114-Status: GOOD ( 23.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Nov 17, 2022 at 09:32:50AM +0800, richard clark wrote: > On Sat, Nov 12, 2022 at 6:40 AM Catalin Marinas wrote: > > On Thu, Nov 10, 2022 at 11:27:23AM +0800, richard clark wrote: > > > On Wed, Nov 9, 2022 at 5:26 PM Catalin Marinas wrote: > > > > On Wed, Nov 09, 2022 at 04:34:13PM +0800, richard clark wrote: > > > > > Suppose in a heterogeneous system, there're cortex-M7 and cortex-A72 > > > > > sharing the same bus. Does the below code sequence work as (ldr/str)ex > > > > > expected? > > > > > > > > > > r2 point to a uncached shared memory between M7 and A72 > > > > > > > > > > M7 A72 > > > > > ldrex r1, [r2] > > > > > -------------------------> strex r0, r1, [r2] > > > > > > > > In general, it won't. The exclusives are supposed to work in the same > > > > inner shareable domain, so it depends on how the SoC has the M7 and A72 > > > > wired up. Are they cache coherent with each-other? Is there a global > > > > exclusive monitor? The M7 may also need the MPU regions set up with the > > > > Shareable attribute. > > > > > > Thanks Catalin! AFAIK the M7 and A53 are not in the same Inner > > > shareable domain: if A53 modifies the SRAM with D$ on, the M7 will > > > still get the stale data from the same SRAM location. Except that > > > probably there is not a global exclusive monitor there. > > > > An SoC may allow exclusives on a small range of non-cacheable memory but > > it's not something to infer from the CPUID registers. You'd have to ask > > the hardware people whether they built a global exclusive monitor and > > whether that's shared with the M7. > > The hardware people confirmed there's no global exclusive monitor in > the SoC and the M and A are not in the same inner-shareable-domain, so > order to access the shared resources between M and A in an exclusive > way, the SoC provides another method as so-called 'hw gate'... You may want to look at hwspinlock and implement a driver that deals with this 'hw gate'. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel