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[34.168.104.7]) by smtp.gmail.com with ESMTPSA id k186-20020a6324c3000000b0046fd180640asm1561643pgk.24.2022.11.17.14.32.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 14:32:56 -0800 (PST) Date: Thu, 17 Nov 2022 22:32:53 +0000 From: Sean Christopherson To: Oliver Upton Cc: Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, Reiji Watanabe Subject: Re: [PATCH 2/2] KVM: arm64: selftests: Disable single-step without relying on ucall() Message-ID: References: <20221117002350.2178351-1-seanjc@google.com> <20221117002350.2178351-3-seanjc@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221117_143259_900033_BDBF2DC8 X-CRM114-Status: GOOD ( 22.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Nov 17, 2022, Sean Christopherson wrote: > On Thu, Nov 17, 2022, Sean Christopherson wrote: > > On Thu, Nov 17, 2022, Oliver Upton wrote: > > > On Thu, Nov 17, 2022 at 12:23:50AM +0000, Sean Christopherson wrote: > > > > Automatically disable single-step when the guest reaches the end of the > > > > verified section instead of using an explicit ucall() to ask userspace to > > > > disable single-step. An upcoming change to implement a pool-based scheme > > > > for ucall() will add an atomic operation (bit test and set) in the guest > > > > ucall code, and if the compiler generate "old school" atomics, e.g. > > > > > > Off topic, but I didn't ask when we were discussing this issue. What is > > > the atomic used for in the pool-based ucall implementation? > > > > To avoid having to plumb an "id" into the guest, vCPUs grab a ucall entry from > > the pool on a first-come first-serve basis, and then release the entry when the > > ucall is complete. The current implementation is a bitmap, e.g. every possible > > entry has a bit in the map, and vCPUs do an atomic bit-test-and-set to claim an > > entry. > > > > Ugh. And there's a bug. Of course I notice it after sending the pull request. > > Depsite being defined in atomic.h, and despite clear_bit() being atomic in the > > kernel, tools' clear_bit() isn't actually atomic. Grr. > > > > Doesn't cause problems because there are so few multi-vCPU selftests, but that > > needs to be fixed. Best thing would be to fix clear_bit() itself. > > Ha! And I bet when clear_bit() is fixed, this test will start failing again > because the ucall() to activate single-step needs to release the entry _after_ > exiting to the host, i.e. single-step will be enabled across the atomic region > again. LOL, yep. Test gets stuck in __aarch64_ldclr8_sync(). _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel