[PATCH 0/8] ARM: Expose Armv8 AArch32 features via hwcap

[PATCH 0/8] ARM: Expose Armv8 AArch32 features via hwcap

[Amit Daniel Kachhap]

Hi All,

This series advertise availability of Armv8 features present in AArch32
state. These features are mostly Advanced SIMD(fphp, asimdhp, dp,
fhm, bf16, i8mm) and few others(sb ssbs). These features are already exposed
to user in arm64 kernel. A similar series advertising the features in
arm64 kernel in compat mode will be sent separately.

Some other remaining features(SPECRES,  ETS, nTLBPA, CSV3, LSMAOC) are not
advertised in arm64 kernel so left here also.

The entire series is divided feature wise as present in Armv8 manual.
The details of these features can be found in Armv8 architecture
reference manual available from
https://developer.arm.com/documentation/ddi0487/gb/?lang=en

All the changes have been tested on Arm FVP Base Revc model after adding
necessary model parameters.

The series is based on Linux 6.1-rc1.

Thanks,
Amit Daniel

Amit Daniel Kachhap (8):
  ARM: Define Armv8 registers in AArch32 state
  ARM: vfp: Add hwcap FPHP and ASIMDHP for FEAT_FP16
  ARM: vfp: Add hwcap for FEAT_DotProd
  ARM: vfp: Add hwcap for FEAT_FHM
  ARM: vfp: Add hwcap for FEAT_AA32BF16
  ARM: vfp: Add hwcap for FEAT_AA32I8MM
  ARM: Add hwcap for Speculation Barrier(SB)
  ARM: Add hwcap for Speculative Store Bypassing Safe

 arch/arm/include/asm/cputype.h    |  4 ++++
 arch/arm/include/asm/vfp.h        |  6 ++++++
 arch/arm/include/uapi/asm/hwcap.h |  8 ++++++++
 arch/arm/kernel/setup.c           | 22 +++++++++++++++++++++
 arch/arm/vfp/vfpmodule.c          | 32 +++++++++++++++++++++++++++++++
 5 files changed, 72 insertions(+)

-- 
2.17.1


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[PATCH 1/8] ARM: Define Armv8 registers in AArch32 state

[Amit Daniel Kachhap]

AArch32 Instruction Set Attribute Register 6 (ID_ISAR6_EL1) and AArch32
Processor Feature Register 2 (ID_PFR2_EL1) identifies some new features
for the Armv8 architecture. This registers will be utilized to add
hwcaps for those cpu features.

These registers are marked as reserved for Armv7 and should be a RAZ.

Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
---
 arch/arm/include/asm/cputype.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 775cac3c02bb..0163c3e78a67 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -25,6 +25,8 @@
 #define CPUID_EXT_ISAR3	0x6c
 #define CPUID_EXT_ISAR4	0x70
 #define CPUID_EXT_ISAR5	0x74
+#define CPUID_EXT_ISAR6	0x7c
+#define CPUID_EXT_PFR2	0x90
 #else
 #define CPUID_EXT_PFR0	"c1, 0"
 #define CPUID_EXT_PFR1	"c1, 1"
@@ -40,6 +42,8 @@
 #define CPUID_EXT_ISAR3	"c2, 3"
 #define CPUID_EXT_ISAR4	"c2, 4"
 #define CPUID_EXT_ISAR5	"c2, 5"
+#define CPUID_EXT_ISAR6	"c2, 7"
+#define CPUID_EXT_PFR2	"c3, 4"
 #endif
 
 #define MPIDR_SMP_BITMASK (0x3 << 30)
-- 
2.17.1


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[PATCH 2/8] ARM: vfp: Add hwcap FPHP and ASIMDHP for FEAT_FP16

[Amit Daniel Kachhap]

Floating point half-precision (FPHP) and Advanced SIMD half-precision
(ASIMDHP) are VFP features (FEAT_FP16) represented by MVFR1 identification
register. These capabilities can optionally exist with VFPv3 and mandatory
with VFPv4. Both these new features exist for Armv8 architecture in AArch32
state.

These hwcaps may be useful for the userspace to add conditional check
before trying to use FEAT_FP16 feature specific instructions.

Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
---
 arch/arm/include/asm/vfp.h        | 6 ++++++
 arch/arm/include/uapi/asm/hwcap.h | 2 ++
 arch/arm/kernel/setup.c           | 2 ++
 arch/arm/vfp/vfpmodule.c          | 4 ++++
 4 files changed, 14 insertions(+)

diff --git a/arch/arm/include/asm/vfp.h b/arch/arm/include/asm/vfp.h
index 19928bfb4f9c..157ea3426158 100644
--- a/arch/arm/include/asm/vfp.h
+++ b/arch/arm/include/asm/vfp.h
@@ -87,6 +87,12 @@
 #define MVFR0_DP_BIT		(8)
 #define MVFR0_DP_MASK		(0xf << MVFR0_DP_BIT)
 
+/* MVFR1 bits */
+#define MVFR1_ASIMDHP_BIT	(20)
+#define MVFR1_ASIMDHP_MASK	(0xf << MVFR1_ASIMDHP_BIT)
+#define MVFR1_FPHP_BIT		(24)
+#define MVFR1_FPHP_MASK		(0xf << MVFR1_FPHP_BIT)
+
 /* Bit patterns for decoding the packaged operation descriptors */
 #define VFPOPDESC_LENGTH_BIT	(9)
 #define VFPOPDESC_LENGTH_MASK	(0x07 << VFPOPDESC_LENGTH_BIT)
diff --git a/arch/arm/include/uapi/asm/hwcap.h b/arch/arm/include/uapi/asm/hwcap.h
index 990199d8b7c6..8b6f690f0ac4 100644
--- a/arch/arm/include/uapi/asm/hwcap.h
+++ b/arch/arm/include/uapi/asm/hwcap.h
@@ -28,6 +28,8 @@
 #define HWCAP_IDIV	(HWCAP_IDIVA | HWCAP_IDIVT)
 #define HWCAP_LPAE	(1 << 20)
 #define HWCAP_EVTSTRM	(1 << 21)
+#define HWCAP_FPHP	(1 << 22)
+#define HWCAP_ASIMDHP	(1 << 23)
 
 /*
  * HWCAP2 flags - for elf_hwcap2 (in kernel) and AT_HWCAP2
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index cb88c6e69377..d675a7618cf4 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -1249,6 +1249,8 @@ static const char *hwcap_str[] = {
 	"vfpd32",
 	"lpae",
 	"evtstrm",
+	"fphp",
+	"asimdhp",
 	NULL
 };
 
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 2cb355c1b5b7..55dcd96c7e3b 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -831,6 +831,10 @@ static int __init vfp_init(void)
 
 			if ((fmrx(MVFR1) & 0xf0000000) == 0x10000000)
 				elf_hwcap |= HWCAP_VFPv4;
+			if (((fmrx(MVFR1) & MVFR1_ASIMDHP_MASK) >> MVFR1_ASIMDHP_BIT) == 0x2)
+				elf_hwcap |= HWCAP_ASIMDHP;
+			if (((fmrx(MVFR1) & MVFR1_FPHP_MASK) >> MVFR1_FPHP_BIT) == 0x3)
+				elf_hwcap |= HWCAP_FPHP;
 		}
 	/* Extract the architecture version on pre-cpuid scheme */
 	} else {
-- 
2.17.1


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[PATCH 3/8] ARM: vfp: Add hwcap for FEAT_DotProd

[Amit Daniel Kachhap]

Advanced Dot product is a feature present in AArch32 state for Armv8 and
is represented by ISAR6 identification register.

This feature denotes the presence of UDOT and SDOT instructions and
hence adding a hwcap will enable the userspace to check it before
trying to use those instructions.

Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
---
 arch/arm/include/uapi/asm/hwcap.h |  1 +
 arch/arm/kernel/setup.c           |  1 +
 arch/arm/vfp/vfpmodule.c          | 10 ++++++++++
 3 files changed, 12 insertions(+)

diff --git a/arch/arm/include/uapi/asm/hwcap.h b/arch/arm/include/uapi/asm/hwcap.h
index 8b6f690f0ac4..64f3608e6f1b 100644
--- a/arch/arm/include/uapi/asm/hwcap.h
+++ b/arch/arm/include/uapi/asm/hwcap.h
@@ -30,6 +30,7 @@
 #define HWCAP_EVTSTRM	(1 << 21)
 #define HWCAP_FPHP	(1 << 22)
 #define HWCAP_ASIMDHP	(1 << 23)
+#define HWCAP_ASIMDDP	(1 << 24)
 
 /*
  * HWCAP2 flags - for elf_hwcap2 (in kernel) and AT_HWCAP2
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index d675a7618cf4..c55ff1110152 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -1251,6 +1251,7 @@ static const char *hwcap_str[] = {
 	"evtstrm",
 	"fphp",
 	"asimdhp",
+	"asimddp",
 	NULL
 };
 
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 55dcd96c7e3b..70f1e0f4eece 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -774,6 +774,7 @@ static int __init vfp_init(void)
 {
 	unsigned int vfpsid;
 	unsigned int cpu_arch = cpu_architecture();
+	unsigned int isar6;
 
 	/*
 	 * Enable the access to the VFP on all online CPUs so the
@@ -836,6 +837,15 @@ static int __init vfp_init(void)
 			if (((fmrx(MVFR1) & MVFR1_FPHP_MASK) >> MVFR1_FPHP_BIT) == 0x3)
 				elf_hwcap |= HWCAP_FPHP;
 		}
+
+		/*
+		 * Check for the presence of Advanced SIMD Dot Product
+		 * instructions.
+		 */
+		isar6 = read_cpuid_ext(CPUID_EXT_ISAR6);
+		if (cpuid_feature_extract_field(isar6, 4) == 0x1)
+			elf_hwcap |= HWCAP_ASIMDDP;
+
 	/* Extract the architecture version on pre-cpuid scheme */
 	} else {
 		if (vfpsid & FPSID_NODOUBLE) {
-- 
2.17.1


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[PATCH 4/8] ARM: vfp: Add hwcap for FEAT_FHM

[Amit Daniel Kachhap]

Floating-point half-precision multiplication (FHM) is a feature present
in AArch32 state for Armv8 and is represented by ISAR6.FHM identification
register.

This feature denotes the presence of VFMAL and VMFSL instructions and
hence adding a hwcap will enable the userspace to check it before
trying to use those instructions.

Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
---
 arch/arm/include/uapi/asm/hwcap.h | 1 +
 arch/arm/kernel/setup.c           | 1 +
 arch/arm/vfp/vfpmodule.c          | 6 ++++++
 3 files changed, 8 insertions(+)

diff --git a/arch/arm/include/uapi/asm/hwcap.h b/arch/arm/include/uapi/asm/hwcap.h
index 64f3608e6f1b..3d168d4f2a51 100644
--- a/arch/arm/include/uapi/asm/hwcap.h
+++ b/arch/arm/include/uapi/asm/hwcap.h
@@ -31,6 +31,7 @@
 #define HWCAP_FPHP	(1 << 22)
 #define HWCAP_ASIMDHP	(1 << 23)
 #define HWCAP_ASIMDDP	(1 << 24)
+#define HWCAP_ASIMDFHM	(1 << 25)
 
 /*
  * HWCAP2 flags - for elf_hwcap2 (in kernel) and AT_HWCAP2
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index c55ff1110152..5e8bf2d5e516 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -1252,6 +1252,7 @@ static const char *hwcap_str[] = {
 	"fphp",
 	"asimdhp",
 	"asimddp",
+	"asimdfhm",
 	NULL
 };
 
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 70f1e0f4eece..404c4f901132 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -845,6 +845,12 @@ static int __init vfp_init(void)
 		isar6 = read_cpuid_ext(CPUID_EXT_ISAR6);
 		if (cpuid_feature_extract_field(isar6, 4) == 0x1)
 			elf_hwcap |= HWCAP_ASIMDDP;
+		/*
+		 * Check for the presence of Advanced SIMD Floating point
+		 * half-precision multiplication instructions.
+		 */
+		if (cpuid_feature_extract_field(isar6, 8) == 0x1)
+			elf_hwcap |= HWCAP_ASIMDFHM;
 
 	/* Extract the architecture version on pre-cpuid scheme */
 	} else {
-- 
2.17.1


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[PATCH 5/8] ARM: vfp: Add hwcap for FEAT_AA32BF16

[Amit Daniel Kachhap]

Advanced SIMD BFloat16 (FEAT_AA32BF16) is a feature present in AArch32
state for Armv8 and is represented by ISAR6.BF16 identification register.

This feature denotes the presence of VCVT, VCVTB, VCVTT, VDOT, VFMAB,
VFMAT and VMMLA instructions and hence adding a hwcap will enable the
userspace to check it before trying to use those instructions.

Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
---
 arch/arm/include/uapi/asm/hwcap.h | 1 +
 arch/arm/kernel/setup.c           | 1 +
 arch/arm/vfp/vfpmodule.c          | 6 ++++++
 3 files changed, 8 insertions(+)

diff --git a/arch/arm/include/uapi/asm/hwcap.h b/arch/arm/include/uapi/asm/hwcap.h
index 3d168d4f2a51..14e260e2d6d0 100644
--- a/arch/arm/include/uapi/asm/hwcap.h
+++ b/arch/arm/include/uapi/asm/hwcap.h
@@ -32,6 +32,7 @@
 #define HWCAP_ASIMDHP	(1 << 23)
 #define HWCAP_ASIMDDP	(1 << 24)
 #define HWCAP_ASIMDFHM	(1 << 25)
+#define HWCAP_ASIMDBF16	(1 << 26)
 
 /*
  * HWCAP2 flags - for elf_hwcap2 (in kernel) and AT_HWCAP2
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 5e8bf2d5e516..231d885ad4b5 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -1253,6 +1253,7 @@ static const char *hwcap_str[] = {
 	"asimdhp",
 	"asimddp",
 	"asimdfhm",
+	"asimdbf16",
 	NULL
 };
 
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 404c4f901132..ff574cb8a0b9 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -851,6 +851,12 @@ static int __init vfp_init(void)
 		 */
 		if (cpuid_feature_extract_field(isar6, 8) == 0x1)
 			elf_hwcap |= HWCAP_ASIMDFHM;
+		/*
+		 * Check for the presence of Advanced SIMD Bfloat16
+		 * floating point instructions.
+		 */
+		if (cpuid_feature_extract_field(isar6, 20) == 0x1)
+			elf_hwcap |= HWCAP_ASIMDBF16;
 
 	/* Extract the architecture version on pre-cpuid scheme */
 	} else {
-- 
2.17.1


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[PATCH 6/8] ARM: vfp: Add hwcap for FEAT_AA32I8MM

[Amit Daniel Kachhap]

Int8 matrix multiplication (FEAT_AA32I8MM) is a feature present in AArch32
state for Armv8 and is represented by ISAR6.I8MM identification register.

This feature denotes the presence of VSMMLA, VSUDOT, VUMMLA, VUSMMLA and
VUSDOT instructions and hence adding a hwcap will enable the userspace
to check it before trying to use those instructions.

Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
---
 arch/arm/include/uapi/asm/hwcap.h | 1 +
 arch/arm/kernel/setup.c           | 1 +
 arch/arm/vfp/vfpmodule.c          | 6 ++++++
 3 files changed, 8 insertions(+)

diff --git a/arch/arm/include/uapi/asm/hwcap.h b/arch/arm/include/uapi/asm/hwcap.h
index 14e260e2d6d0..46833c668ec2 100644
--- a/arch/arm/include/uapi/asm/hwcap.h
+++ b/arch/arm/include/uapi/asm/hwcap.h
@@ -33,6 +33,7 @@
 #define HWCAP_ASIMDDP	(1 << 24)
 #define HWCAP_ASIMDFHM	(1 << 25)
 #define HWCAP_ASIMDBF16	(1 << 26)
+#define HWCAP_I8MM	(1 << 27)
 
 /*
  * HWCAP2 flags - for elf_hwcap2 (in kernel) and AT_HWCAP2
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 231d885ad4b5..de2d85ddec8d 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -1254,6 +1254,7 @@ static const char *hwcap_str[] = {
 	"asimddp",
 	"asimdfhm",
 	"asimdbf16",
+	"i8mm",
 	NULL
 };
 
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index ff574cb8a0b9..281110423871 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -857,6 +857,12 @@ static int __init vfp_init(void)
 		 */
 		if (cpuid_feature_extract_field(isar6, 20) == 0x1)
 			elf_hwcap |= HWCAP_ASIMDBF16;
+		/*
+		 * Check for the presence of Advanced SIMD and floating point
+		 * Int8 matrix multiplication instructions instructions.
+		 */
+		if (cpuid_feature_extract_field(isar6, 24) == 0x1)
+			elf_hwcap |= HWCAP_I8MM;
 
 	/* Extract the architecture version on pre-cpuid scheme */
 	} else {
-- 
2.17.1


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[PATCH 7/8] ARM: Add hwcap for Speculation Barrier(SB)

[Amit Daniel Kachhap]

Speculation Barrier(FEAT_SB) is a feature present in AArch32 state for
Armv8 and is represented by ISAR6.SB identification register.

This feature denotes the presence of SB instruction and hence adding a
hwcap will enable the userspace to check it before trying to use this
instruction.

This commit adds the ID feature bit detection, and uses elf_hwcap2
accordingly.

Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
---
 arch/arm/include/uapi/asm/hwcap.h | 1 +
 arch/arm/kernel/setup.c           | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/arch/arm/include/uapi/asm/hwcap.h b/arch/arm/include/uapi/asm/hwcap.h
index 46833c668ec2..bc9e7d318e25 100644
--- a/arch/arm/include/uapi/asm/hwcap.h
+++ b/arch/arm/include/uapi/asm/hwcap.h
@@ -43,5 +43,6 @@
 #define HWCAP2_SHA1	(1 << 2)
 #define HWCAP2_SHA2	(1 << 3)
 #define HWCAP2_CRC32	(1 << 4)
+#define HWCAP2_SB	(1 << 5)
 
 #endif /* _UAPI__ASMARM_HWCAP_H */
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index de2d85ddec8d..f676c54e5d14 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -450,6 +450,7 @@ static void __init cpuid_init_hwcaps(void)
 {
 	int block;
 	u32 isar5;
+	u32 isar6;
 
 	if (cpu_architecture() < CPU_ARCH_ARMv7)
 		return;
@@ -485,6 +486,12 @@ static void __init cpuid_init_hwcaps(void)
 	block = cpuid_feature_extract_field(isar5, 16);
 	if (block >= 1)
 		elf_hwcap2 |= HWCAP2_CRC32;
+
+	/* Check for Speculation barrier instruction */
+	isar6 = read_cpuid_ext(CPUID_EXT_ISAR6);
+	block = cpuid_feature_extract_field(isar6, 12);
+	if (block >= 1)
+		elf_hwcap2 |= HWCAP2_SB;
 }
 
 static void __init elf_hwcap_fixup(void)
@@ -1264,6 +1271,7 @@ static const char *hwcap2_str[] = {
 	"sha1",
 	"sha2",
 	"crc32",
+	"sb",
 	NULL
 };
 
-- 
2.17.1


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Re: [PATCH 7/8] ARM: Add hwcap for Speculation Barrier(SB)

[Linus Walleij]

On Wed, Oct 26, 2022 at 7:53 AM Amit Daniel Kachhap
<amit.kachhap@arm.com> wrote:

> Speculation Barrier(FEAT_SB) is a feature present in AArch32 state for
> Armv8 and is represented by ISAR6.SB identification register.
>
> This feature denotes the presence of SB instruction and hence adding a
> hwcap will enable the userspace to check it before trying to use this
> instruction.
>
> This commit adds the ID feature bit detection, and uses elf_hwcap2
> accordingly.
>
> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>

The patch is fine, the following is a question.

I see that the aarch64 kernel is using this instruction in the kernel
for speculation barriers, and after this the aarch32 userspace can
use it too.

Does it make sense to ask the question whether this could be
compiled into and used by a aarch32 kernel, provided it is
configured for a core known to support it? (This is assuming that
the compiler also knows about it.)

I'm asking because speculation barriers is something we have a
lot of due to the constant security problems so it might be something
handy to have in the toolbox.

It might be just adding too much complexity... I know.

Yours,
Linus Walleij

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Re: [PATCH 7/8] ARM: Add hwcap for Speculation Barrier(SB)

[Amit Daniel Kachhap]

On 11/16/22 19:36, Linus Walleij wrote:
> On Wed, Oct 26, 2022 at 7:53 AM Amit Daniel Kachhap
> <amit.kachhap@arm.com> wrote:
> 
>> Speculation Barrier(FEAT_SB) is a feature present in AArch32 state for
>> Armv8 and is represented by ISAR6.SB identification register.
>>
>> This feature denotes the presence of SB instruction and hence adding a
>> hwcap will enable the userspace to check it before trying to use this
>> instruction.
>>
>> This commit adds the ID feature bit detection, and uses elf_hwcap2
>> accordingly.
>>
>> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
> 
> The patch is fine, the following is a question.
> 
> I see that the aarch64 kernel is using this instruction in the kernel
> for speculation barriers, and after this the aarch32 userspace can
> use it too.
> 
> Does it make sense to ask the question whether this could be
> compiled into and used by a aarch32 kernel, provided it is
> configured for a core known to support it? (This is assuming that
> the compiler also knows about it.)

I think you have a valid point to use sb in the kernel also. Besides the
compiler support, aarch32 kernel might need feature based dynamic
instruction patching framework like aarch64. So as you said it is too
much to do here.

Thanks,
Amit Daniel
> 
> I'm asking because speculation barriers is something we have a
> lot of due to the constant security problems so it might be something
> handy to have in the toolbox.
> 
> It might be just adding too much complexity... I know.
> 
> Yours,
> Linus Walleij

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Re: [PATCH 7/8] ARM: Add hwcap for Speculation Barrier(SB)

[Robin Murphy]

On 2022-11-16 14:06, Linus Walleij wrote:
> On Wed, Oct 26, 2022 at 7:53 AM Amit Daniel Kachhap
> <amit.kachhap@arm.com> wrote:
> 
>> Speculation Barrier(FEAT_SB) is a feature present in AArch32 state for
>> Armv8 and is represented by ISAR6.SB identification register.
>>
>> This feature denotes the presence of SB instruction and hence adding a
>> hwcap will enable the userspace to check it before trying to use this
>> instruction.
>>
>> This commit adds the ID feature bit detection, and uses elf_hwcap2
>> accordingly.
>>
>> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
> 
> The patch is fine, the following is a question.
> 
> I see that the aarch64 kernel is using this instruction in the kernel
> for speculation barriers, and after this the aarch32 userspace can
> use it too.
> 
> Does it make sense to ask the question whether this could be
> compiled into and used by a aarch32 kernel, provided it is
> configured for a core known to support it? (This is assuming that
> the compiler also knows about it.)
> 
> I'm asking because speculation barriers is something we have a
> lot of due to the constant security problems so it might be something
> handy to have in the toolbox.
> 
> It might be just adding too much complexity... I know.

Certainly none of Arm's CPUs new enough to implement FEAT_SB still 
support AArch32 at EL1.

Robin.

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[PATCH 8/8] ARM: Add hwcap for Speculative Store Bypassing Safe

[Amit Daniel Kachhap]

Speculative Store Bypassing Safe(FEAT_SSBS) is a feature present in
AArch32 state for Armv8 and is represented by ID_PFR2_EL1.SSBS
identification register.

This feature denotes the presence of PSTATE.ssbs bit and hence adding a
hwcap will enable the userspace to check it before trying to set/unset this
PSTATE.

This commit adds the ID feature bit detection, and uses elf_hwcap2
accordingly.

Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
---
 arch/arm/include/uapi/asm/hwcap.h | 1 +
 arch/arm/kernel/setup.c           | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/arch/arm/include/uapi/asm/hwcap.h b/arch/arm/include/uapi/asm/hwcap.h
index bc9e7d318e25..6b2023e39b6f 100644
--- a/arch/arm/include/uapi/asm/hwcap.h
+++ b/arch/arm/include/uapi/asm/hwcap.h
@@ -44,5 +44,6 @@
 #define HWCAP2_SHA2	(1 << 3)
 #define HWCAP2_CRC32	(1 << 4)
 #define HWCAP2_SB	(1 << 5)
+#define HWCAP2_SSBS	(1 << 6)
 
 #endif /* _UAPI__ASMARM_HWCAP_H */
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index f676c54e5d14..75cd4699e7b3 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -451,6 +451,7 @@ static void __init cpuid_init_hwcaps(void)
 	int block;
 	u32 isar5;
 	u32 isar6;
+	u32 pfr2;
 
 	if (cpu_architecture() < CPU_ARCH_ARMv7)
 		return;
@@ -492,6 +493,12 @@ static void __init cpuid_init_hwcaps(void)
 	block = cpuid_feature_extract_field(isar6, 12);
 	if (block >= 1)
 		elf_hwcap2 |= HWCAP2_SB;
+
+	/* Check for Speculative Store Bypassing control */
+	pfr2 = read_cpuid_ext(CPUID_EXT_PFR2);
+	block = cpuid_feature_extract_field(pfr2, 4);
+	if (block >= 1)
+		elf_hwcap2 |= HWCAP2_SSBS;
 }
 
 static void __init elf_hwcap_fixup(void)
@@ -1272,6 +1279,7 @@ static const char *hwcap2_str[] = {
 	"sha2",
 	"crc32",
 	"sb",
+	"ssbs",
 	NULL
 };
 
-- 
2.17.1


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Re: [PATCH 0/8] ARM: Expose Armv8 AArch32 features via hwcap

[Linus Walleij]

On Wed, Oct 26, 2022 at 7:51 AM Amit Daniel Kachhap
<amit.kachhap@arm.com> wrote:

> This series advertise availability of Armv8 features present in AArch32
> state. These features are mostly Advanced SIMD(fphp, asimdhp, dp,
> fhm, bf16, i8mm) and few others(sb ssbs). These features are already exposed
> to user in arm64 kernel. A similar series advertising the features in
> arm64 kernel in compat mode will be sent separately.
>
> Some other remaining features(SPECRES,  ETS, nTLBPA, CSV3, LSMAOC) are not
> advertised in arm64 kernel so left here also.
>
> The entire series is divided feature wise as present in Armv8 manual.
> The details of these features can be found in Armv8 architecture
> reference manual available from
> https://developer.arm.com/documentation/ddi0487/gb/?lang=en
>
> All the changes have been tested on Arm FVP Base Revc model after adding
> necessary model parameters.

These all make sense and the patches are fairly trivial, so:
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

I was just looking at Marcins feature matrix of some systems found
in the wild to see which systems will benefit from this and it includes
Apple M1 and other interesting stuff:
https://marcin.juszkiewicz.com.pl/download/tables/arm-socs.html

Can you please put these patches into Russell's patch tracker?

I might add some comment to some patch just for discussion
but the patches are fine.

Yours,
Linus Walleij

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Re: [PATCH 0/8] ARM: Expose Armv8 AArch32 features via hwcap

[Amit Kachhap]

On 11/16/22 19:21, Linus Walleij wrote:
> On Wed, Oct 26, 2022 at 7:51 AM Amit Daniel Kachhap
> <amit.kachhap@arm.com> wrote:
> 
>> This series advertise availability of Armv8 features present in AArch32
>> state. These features are mostly Advanced SIMD(fphp, asimdhp, dp,
>> fhm, bf16, i8mm) and few others(sb ssbs). These features are already exposed
>> to user in arm64 kernel. A similar series advertising the features in
>> arm64 kernel in compat mode will be sent separately.
>>
>> Some other remaining features(SPECRES,  ETS, nTLBPA, CSV3, LSMAOC) are not
>> advertised in arm64 kernel so left here also.
>>
>> The entire series is divided feature wise as present in Armv8 manual.
>> The details of these features can be found in Armv8 architecture
>> reference manual available from
>> https://developer.arm.com/documentation/ddi0487/gb/?lang=en
>>
>> All the changes have been tested on Arm FVP Base Revc model after adding
>> necessary model parameters.
> 
> These all make sense and the patches are fairly trivial, so:
> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
> 
> I was just looking at Marcins feature matrix of some systems found
> in the wild to see which systems will benefit from this and it includes
> Apple M1 and other interesting stuff:
> https://marcin.juszkiewicz.com.pl/download/tables/arm-socs.html
> 
> Can you please put these patches into Russell's patch tracker?

Thanks for the feedback. I submitted them to Russell's patch tracker
with your Reviewed-by.

Amit
> 
> I might add some comment to some patch just for discussion
> but the patches are fine.
> 
> Yours,
> Linus Walleij

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Re: [PATCH 0/8] ARM: Expose Armv8 AArch32 features via hwcap

[Russell King (Oracle)]

On Wed, Oct 26, 2022 at 11:19:53AM +0530, Amit Daniel Kachhap wrote:
> Hi All,
> 
> This series advertise availability of Armv8 features present in AArch32
> state. These features are mostly Advanced SIMD(fphp, asimdhp, dp,
> fhm, bf16, i8mm) and few others(sb ssbs). These features are already exposed
> to user in arm64 kernel. A similar series advertising the features in
> arm64 kernel in compat mode will be sent separately.
> 
> Some other remaining features(SPECRES,  ETS, nTLBPA, CSV3, LSMAOC) are not
> advertised in arm64 kernel so left here also.
> 
> The entire series is divided feature wise as present in Armv8 manual.
> The details of these features can be found in Armv8 architecture
> reference manual available from
> https://developer.arm.com/documentation/ddi0487/gb/?lang=en
> 
> All the changes have been tested on Arm FVP Base Revc model after adding
> necessary model parameters.
> 
> The series is based on Linux 6.1-rc1.

Hi Amit,

Please could you list which CPUs support running aarch32 _and_ support
these features?

Thanks!

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Re: [PATCH 0/8] ARM: Expose Armv8 AArch32 features via hwcap

[Amit Daniel Kachhap]

On 11/22/22 00:34, Russell King (Oracle) wrote:
> On Wed, Oct 26, 2022 at 11:19:53AM +0530, Amit Daniel Kachhap wrote:
>> Hi All,
>> 
>> This series advertise availability of Armv8 features present in
>> AArch32 state. These features are mostly Advanced SIMD(fphp,
>> asimdhp, dp, fhm, bf16, i8mm) and few others(sb ssbs). These
>> features are already exposed to user in arm64 kernel. A similar
>> series advertising the features in arm64 kernel in compat mode will
>> be sent separately.
>> 
>> Some other remaining features(SPECRES,  ETS, nTLBPA, CSV3, LSMAOC)
>> are not advertised in arm64 kernel so left here also.
>> 
>> The entire series is divided feature wise as present in Armv8
>> manual. The details of these features can be found in Armv8
>> architecture reference manual available from 
>> https://developer.arm.com/documentation/ddi0487/gb/?lang=en
>> 
>> All the changes have been tested on Arm FVP Base Revc model after
>> adding necessary model parameters.
>> 
>> The series is based on Linux 6.1-rc1.
> 
> Hi Amit,
> 
> Please could you list which CPUs support running aarch32 _and_
> support these features?
> 
> Thanks!

Hi Russell,

Below are some of the cpus representing these AArch32 features. This
list is not exhaustive enough and can be found in the respective
processor manual.


Features-

fp16(fphp+asimdhp):
Architectures       - v8.2(optional)
AArch32 Processor   - Cortex A75 and A55 at all el, A710 and Neoverse N2 
at el0 only

dp:
Architectures       - v8.2(optional), v8.4(mandatory)
AArch32 Processor   - Cortex A75 and A55 at all el, A710 and Neoverse N2 
at el0 only

fhm:
Architectures       - v8.2(optional), v8.4(mandatory)
AArch32 Processor   - Cortex A710 and Neoverse N2 at el0 only

aa32bf16:
Architectures       - v8.2(optional)
AArch32 Processor   - Cortex A710 and Neoverse N2 at el0 only

aa32i8mm:
Architectures       - v8.2(optional), v8.4(mandatory)
AArch32 Processor   - Cortex A710 and Neoverse N2 at el0 only

sb:
Architectures       - v8.0(optional),v8.5(Mandatory)
AArch32 Processor   - Cortex A710 and Neoverse N2 at el0 only

ssbs:
Architectures       - v8.0(Optional), v8.5(Mandatory)
AArch32 Processor   - Cortex A76, A710 and Neoverse N2 at el0 only

Thanks,
Amit


> 

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