From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 78078C4332F for ; Tue, 22 Nov 2022 03:15:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:CC:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=CwKEPaucr6G0U3azAF26Kq/Mvk/pnng8E0GAVUxm3wc=; b=MwjYfyzfPXm9HG Ja0YmwZF1BRtXHqnbVxk40m+avDjDPNwfOE1UZ+W0bjZ6LtEHxopLD8r5fJn4mzwDoMEtMCcpWDXK iXBq4xHO5XRq2soLD76wPWvVwRZ2tfJNvDaCjYz0SaGRbGo59/bY2yPJ3bxwtK1hfK68HCOnRWoY0 Fbq/4fuJ34lgb7ZEps7XfsElWfl67Ycvm8CwlTEKeLS6cnhXmfQpp9QC04Fe6ljEdw3Kx20ynzEYh F69xTNBPeVnnjfj1IodVeKb7SHOB4xL9DN7j7opkYu1C+RWdD5DAiNtlUlGvJrttcZSdy4vdUiXQq scPujpx+mJX5yiAWufDQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oxJjT-002xpt-8W; Tue, 22 Nov 2022 03:13:59 +0000 Received: from lelv0143.ext.ti.com ([198.47.23.248]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oxJjP-002xje-81 for linux-arm-kernel@lists.infradead.org; Tue, 22 Nov 2022 03:13:57 +0000 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2AM3DlYu008487; Mon, 21 Nov 2022 21:13:47 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1669086827; bh=TKEbhj1suQCIIV1Fk7hur1T6VW/Gs8A83nLvMiQ/5u4=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=iRyshwd+3ylMP7KD5ULJ8zdk7c+mEL73bpS6cd5gnZBKNPrHDMXxwBNMfS3pW6lRW 5zms1JzESFTzxx+9roMNmtsNtWoDJE40JcaGVfQU2t7PdyW4jiVjoj79z0Q1nKOynv 4GOOk0jvRwYBXxavI1/NARfEQXUoqNavatQno3FY= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2AM3DlxP012352 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 21 Nov 2022 21:13:47 -0600 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Mon, 21 Nov 2022 21:13:47 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Mon, 21 Nov 2022 21:13:47 -0600 Received: from ubuntu (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with SMTP id 2AM3DZl2094840; Mon, 21 Nov 2022 21:13:37 -0600 Date: Mon, 21 Nov 2022 19:13:34 -0800 From: Matt Ranostay To: Andrew Davis CC: , , , , , , , , , Subject: Re: [PATCH v6 7/8] arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node Message-ID: References: <20221119040906.9495-1-mranostay@ti.com> <20221119040906.9495-8-mranostay@ti.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221121_191355_426995_74E3232C X-CRM114-Status: GOOD ( 25.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Nov 21, 2022 at 11:12:18AM -0600, Andrew Davis wrote: > On 11/18/22 10:09 PM, Matt Ranostay wrote: > > From: Aswath Govindraju > > > > Add PCIe device tree node (both RC and EP) for the single PCIe > > instance present in j721s2. > > > > So which is it, you have two nodes but this is one device. It can > switch between the two modes, a property should have been used to > select the mode for the device. > > Making two nodes for the same device as examples of what they could > look like, then only enabling one of the two in the board level DT > is not how this is done anywhere else. Take the common parts and > make one node here with those. Then at the board level .dts where we > select what mode this driver will act in, add the specific bits for > the chosen mode. > This isn't how it is done in k3-j7200-common-proc-board.dts and k3-j7200-main.dtsi Now I'm fine with making it common node if that is way to go.. - Matt > Andrew > > > Reviewed-by: Siddharth Vadapalli > > Signed-off-by: Aswath Govindraju > > Signed-off-by: Vignesh Raghavendra > > Signed-off-by: Matt Ranostay > > --- > > arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 61 ++++++++++++++++++++++ > > 1 file changed, 61 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi > > index adbb172658b9..04294e25d587 100644 > > --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi > > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi > > @@ -841,6 +841,67 @@ serdes0: serdes@5060000 { > > }; > > }; > > + pcie1_rc: pcie@2910000 { > > + compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; > > + reg = <0x00 0x02910000 0x00 0x1000>, > > + <0x00 0x02917000 0x00 0x400>, > > + <0x00 0x0d800000 0x00 0x00800000>, > > + <0x00 0x18000000 0x00 0x00001000>; > > + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; > > + interrupt-names = "link_state"; > > + interrupts = ; > > + device_type = "pci"; > > + ti,syscon-pcie-ctrl = <&scm_conf 0x074>; > > + max-link-speed = <3>; > > + num-lanes = <4>; > > + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; > > + clocks = <&k3_clks 276 41>; > > + clock-names = "fck"; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + bus-range = <0x0 0xff>; > > + vendor-id = <0x104c>; > > + device-id = <0xb013>; > > + msi-map = <0x0 &gic_its 0x0 0x10000>; > > + dma-coherent; > > + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, > > + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; > > + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; > > + #interrupt-cells = <1>; > > + interrupt-map-mask = <0 0 0 7>; > > + interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */ > > + <0 0 0 2 &pcie1_intc 0>, /* INT B */ > > + <0 0 0 3 &pcie1_intc 0>, /* INT C */ > > + <0 0 0 4 &pcie1_intc 0>; /* INT D */ > > + > > + pcie1_intc: interrupt-controller { > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + interrupt-parent = <&gic500>; > > + interrupts = ; > > + }; > > + }; > > + > > + pcie1_ep: pcie-ep@2910000 { > > + compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; > > + reg = <0x00 0x02910000 0x00 0x1000>, > > + <0x00 0x02917000 0x00 0x400>, > > + <0x00 0x0d800000 0x00 0x00800000>, > > + <0x00 0x18000000 0x00 0x08000000>; > > + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; > > + interrupt-names = "link_state"; > > + interrupts = ; > > + ti,syscon-pcie-ctrl = <&scm_conf 0x074>; > > + max-link-speed = <3>; > > + num-lanes = <4>; > > + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; > > + clocks = <&k3_clks 276 41>; > > + clock-names = "fck"; > > + max-functions = /bits/ 8 <6>; > > + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; > > + dma-coherent; > > + }; > > + > > main_mcan0: can@2701000 { > > compatible = "bosch,m_can"; > > reg = <0x00 0x02701000 0x00 0x200>, _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel