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[69.109.179.158]) by smtp.gmail.com with ESMTPSA id m125-20020a378a83000000b006cbc6e1478csm11642208qkd.57.2022.11.23.06.40.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Nov 2022 06:40:29 -0800 (PST) Date: Tue, 22 Nov 2022 02:27:50 -0500 From: William Breathitt Gray To: Fabrice Gasnier Cc: jic23@kernel.org, alexandre.torgue@foss.st.com, olivier.moysan@foss.st.com, linux-iio@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] counter: stm32-lptimer-cnt: fix the check on arr and cmp registers update Message-ID: References: <20221123133609.465614-1-fabrice.gasnier@foss.st.com> MIME-Version: 1.0 In-Reply-To: <20221123133609.465614-1-fabrice.gasnier@foss.st.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221123_064033_325905_943529D0 X-CRM114-Status: GOOD ( 21.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============2665401220495251249==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============2665401220495251249== Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="0mgwEUJf1fyfHdJ1" Content-Disposition: inline --0mgwEUJf1fyfHdJ1 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Nov 23, 2022 at 02:36:09PM +0100, Fabrice Gasnier wrote: > The ARR (auto reload register) and CMP (compare) registers are > successively written. The status bits to check the update of these > registers are polled together with regmap_read_poll_timeout(). > The condition to end the loop may become true, even if one of the register > isn't correctly updated. > So ensure both status bits are set before clearing them. >=20 > Fixes: d8958824cf07 ("iio: counter: Add support for STM32 LPTimer") > Signed-off-by: Fabrice Gasnier > --- > drivers/counter/stm32-lptimer-cnt.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/drivers/counter/stm32-lptimer-cnt.c b/drivers/counter/stm32-= lptimer-cnt.c > index d6b80b6dfc28..8439755559b2 100644 > --- a/drivers/counter/stm32-lptimer-cnt.c > +++ b/drivers/counter/stm32-lptimer-cnt.c > @@ -69,7 +69,7 @@ static int stm32_lptim_set_enable_state(struct stm32_lp= tim_cnt *priv, > =20 > /* ensure CMP & ARR registers are properly written */ > ret =3D regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, > - (val & STM32_LPTIM_CMPOK_ARROK), > + (val & STM32_LPTIM_CMPOK_ARROK) =3D=3D STM32_LPTIM_CMPOK_ARRO= K, This is a reasonable fix, but I don't like seeing so much happening in an argument list -- it's easy to misunderstand what's going on which can lead to further bugs the future. Pull out this condition to a dedicated bool variable with a comment explaining why we need the equivalence check (i.e. to ensure both status bits are set and not just one). William Breathitt Gray --0mgwEUJf1fyfHdJ1 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEARYKAB0WIQSNN83d4NIlKPjon7a1SFbKvhIjKwUCY3x59gAKCRC1SFbKvhIj K6m4AQDYJtNkjZVyUJNcrrWZaOlUfodLz2Yx1BuFjg5YDeGpZAEA7CMFKO+r2JFh jyelDpd6Evs3sxh1gwWAWDB4cv5E1gk= =eIOy -----END PGP SIGNATURE----- --0mgwEUJf1fyfHdJ1-- --===============2665401220495251249== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============2665401220495251249==--