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[213.179.129.39]) by smtp.gmail.com with ESMTPSA id cm10-20020a0564020c8a00b0046c4553010fsm456932edb.1.2022.12.09.02.01.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Dec 2022 02:01:59 -0800 (PST) Date: Fri, 9 Dec 2022 11:01:58 +0100 From: Jiri Pirko To: "Kubalewski, Arkadiusz" Cc: Vadim Fedorenko , Jakub Kicinski , Jonathan Lemon , Paolo Abeni , "netdev@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-clk@vger.kernel.org" Subject: Re: [RFC PATCH v4 0/4] Create common DPLL/clock configuration API Message-ID: References: <20221129213724.10119-1-vfedorenko@novek.ru> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221209_020205_161177_86B58083 X-CRM114-Status: GOOD ( 11.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Fri, Dec 09, 2022 at 12:05:43AM CET, arkadiusz.kubalewski@intel.com wrote: >>From: Jiri Pirko >>Sent: Thursday, December 8, 2022 12:59 PM >> >>>>From: Jiri Pirko >>>>Sent: Friday, December 2, 2022 5:12 PM >>>> >>>>Fri, Dec 02, 2022 at 12:27:24PM CET, arkadiusz.kubalewski@intel.com >>wrote: >>>>>>From: Jiri Pirko >>>>>>Sent: Wednesday, November 30, 2022 1:32 PM >>>>>> >>>>>>Tue, Nov 29, 2022 at 10:37:20PM CET, vfedorenko@novek.ru wrote: [...] >>>>This you have to clearly specify when you define driver API. >>>>This const attrs should be passed during pin creation/registration. >>>> >>>>Talking about dpll instance itself, the clock_id, clock_quality, these >>>>should be also const attrs. >>>> >>> >>>Actually, clock_quality can also vary on runtime (i.e. ext/synce). We >>cannot >>>determine what Quality Level signal user has connected to the SMA or was >>>received from the network. Only gnss/oscilattor could have const depending >>>on used HW. But generally it shall not be const. >> >>Sec. I'm talkign about the actual dpll quality, means the internal >>clock. How it can vary? > >Yes, the DPLL has some holdover capacity, thus can translate this into QL and >it shall not ever change. Sure, we could add this. > >I was thinking about a source Quality Level. If that would be available here, >the ptp-profiles implementation would be simpler, as ptp daemon could read it >and embed that information in its frames. >Although, this would have to be configurable from user space, at least for EXT >and SYNCE pin types. The kernel would serve as a holder or info shared from one daemon to another one. That does not sound correct. PTP should ask SyncE deamon directly, I believe. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel