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Received: from foss.arm.com ([217.140.110.172]) by desiato.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pDSZ5-001SLW-17 for linux-arm-kernel@lists.infradead.org; Thu, 05 Jan 2023 15:54:01 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 30FD31063; Thu, 5 Jan 2023 07:54:40 -0800 (PST) Received: from FVFF77S0Q05N (unknown [10.57.45.56]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4A3AE3F71A; Thu, 5 Jan 2023 07:53:57 -0800 (PST) Date: Thu, 5 Jan 2023 15:53:48 +0000 From: Mark Rutland To: Marc Zyngier Cc: Will Deacon , linux-arm-kernel@lists.infradead.org, Dmitry Baryshkov , Lorenzo Pieralisi , Arnd Bergmann Subject: Re: [PATCH] firmware/psci: Fix MEM_PROTECT_RANGE function numbers Message-ID: References: <20221125101826.22404-1-will@kernel.org> <86r0w9nfqc.wl-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <86r0w9nfqc.wl-maz@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230105_155359_651694_5908C503 X-CRM114-Status: GOOD ( 20.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jan 05, 2023 at 03:49:47PM +0000, Marc Zyngier wrote: > On Fri, 25 Nov 2022 10:18:26 +0000, > Will Deacon wrote: > > > > PSCI v1.1 offers 32-bit and 64-bit variants of the MEM_PROTECT_RANGE > > call using function identifier 20. > > > > Fix the incorrect definitions of the MEM_PROTECT_CHECK_RANGE calls in > > the PSCI UAPI header. > > > > Cc: Dmitry Baryshkov > > Cc: Mark Rutland > > Cc: Lorenzo Pieralisi > > Cc: Arnd Bergmann > > Fixes: 3137f2e60098 ("firmware/psci: Add debugfs support to ease debugging") > > Signed-off-by: Will Deacon > > --- > > include/uapi/linux/psci.h | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/include/uapi/linux/psci.h b/include/uapi/linux/psci.h > > index 3511095c2702..42a40ad3fb62 100644 > > --- a/include/uapi/linux/psci.h > > +++ b/include/uapi/linux/psci.h > > @@ -58,7 +58,7 @@ > > > > #define PSCI_1_1_FN_SYSTEM_RESET2 PSCI_0_2_FN(18) > > #define PSCI_1_1_FN_MEM_PROTECT PSCI_0_2_FN(19) > > -#define PSCI_1_1_FN_MEM_PROTECT_CHECK_RANGE PSCI_0_2_FN(19) > > +#define PSCI_1_1_FN_MEM_PROTECT_CHECK_RANGE PSCI_0_2_FN(20) > > > > #define PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND PSCI_0_2_FN64(12) > > #define PSCI_1_0_FN64_NODE_HW_STATE PSCI_0_2_FN64(13) > > @@ -67,7 +67,7 @@ > > #define PSCI_1_0_FN64_STAT_COUNT PSCI_0_2_FN64(17) > > > > #define PSCI_1_1_FN64_SYSTEM_RESET2 PSCI_0_2_FN64(18) > > -#define PSCI_1_1_FN64_MEM_PROTECT_CHECK_RANGE PSCI_0_2_FN64(19) > > +#define PSCI_1_1_FN64_MEM_PROTECT_CHECK_RANGE PSCI_0_2_FN64(20) > > > > /* PSCI v0.2 power state encoding for CPU_SUSPEND function */ > > #define PSCI_0_2_POWER_STATE_ID_MASK 0xffff > > Acked-by: Marc Zyngier Likewise: Acked-by: Mark Rutland > Should this be taken via the arm64 tree, together with [1]? Yes please to both being queued via the arm64 tree. Sorry for droppnig the ball here. Going forward I'll try to be explicit w.r.t. how to queue PSCI bits; I'd be happy to route them through arm64 generally if that arm64 maintainers are happy with that. Thanks, Mark. > > Thanks, > > M. > > [1] https://lore.kernel.org/r/20230105090834.630238-1-maz@kernel.org > > -- > Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel