From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1DFE3C54E94 for ; Wed, 25 Jan 2023 18:06:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=OZ5N/mzuZdqD41pM6Wz3UXLLOCbPgIAi/i259SYJESc=; b=so6GJV7N92pFOB wWBrQ+NFhNt9SiaWRcVCuYnLUk1Oj1H9gkBVTiKrZa5wPDZESBESBm3QMF0Fu5harkIiFiMVX+s5v OOhEvb4zVsQkeYfEwydMLfAzCyR2Y2IyDpI5G3zpf8abni/UmXX/a+TL6TDBAdm1R4oUGG5VoGNfM cqWD/7EikUwR3fUflGIga11rCuy8fJ5TZcUPFHLp5UmtOM5zdp+MdmqHzHU+cr1W62q7dizQKxf1u q1uMlAR/H4+lkNYBaF3uqsQBq0Mxie3CgBBD8rmuR5esibBT05xRQgvXLlxeU3z7YcACZSRRE9E9z i5dIrFYCG/yFogf6togA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pKk9C-008Hhj-SC; Wed, 25 Jan 2023 18:05:22 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pKk98-008Hfu-W4 for linux-arm-kernel@lists.infradead.org; Wed, 25 Jan 2023 18:05:21 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 433074B3; Wed, 25 Jan 2023 10:05:55 -0800 (PST) Received: from monolith.localdoman (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 49E923F5A1; Wed, 25 Jan 2023 10:05:12 -0800 (PST) Date: Wed, 25 Jan 2023 18:05:09 +0000 From: Alexandru Elisei To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, broonie@kernel.org, catalin.marinas@arm.com, maz@kernel.org, will@kernel.org Subject: Re: [PATCH v2 3/5] arm64: make ARM64_HAS_GIC_PRIO_MASKING depend on ARM64_HAS_GIC_PRIO_MASKING Message-ID: References: <20230125163826.496739-1-mark.rutland@arm.com> <20230125163826.496739-4-mark.rutland@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230125163826.496739-4-mark.rutland@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230125_100519_115431_FFDD41FE X-CRM114-Status: GOOD ( 26.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, Very low hanging fruit here, but I think you wanted the commit subject to say that ARM64_HAS_GIC_PRIO_MASKING should depend on ARM64_HAS_GIC_CPUIF_SYSREGS instead of depending on itself. Thanks, Alex On Wed, Jan 25, 2023 at 04:38:24PM +0000, Mark Rutland wrote: > Currently the arm64_cpu_capabilities structure for > ARM64_HAS_GIC_PRIO_MASKING open-codes the same CPU field definitions as > the arm64_cpu_capabilities structure for ARM64_HAS_GIC_CPUIF_SYSREGS, so > that can_use_gic_priorities() can use has_useable_gicv3_cpuif(). > > This duplication isn't ideal for the legibility of the code, and sets a > bad example for any ARM64_HAS_GIC_* definitions added by subsequent > patches. > > Instead, have ARM64_HAS_GIC_PRIO_MASKING check for the > ARM64_HAS_GIC_CPUIF_SYSREGS cpucap, and add a comment explaining why > this is safe. Subsequent patches will use the same pattern where one > cpucap depends upon another. > > There should be no functional change as a result of this patch. > > Signed-off-by: Mark Rutland > Cc: Catalin Marinas > Cc: Marc Zyngier > Cc: Mark Brown > Cc: Will Deacon > --- > arch/arm64/kernel/cpufeature.c | 15 +++++++++------ > 1 file changed, 9 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index afd547a5309c7..515975f42d037 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2046,7 +2046,15 @@ early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); > static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, > int scope) > { > - return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope); > + /* > + * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU > + * feature, so will be detected earlier. > + */ > + BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS); > + if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS)) > + return false; > + > + return enable_pseudo_nmi; > } > #endif > > @@ -2537,11 +2545,6 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .capability = ARM64_HAS_GIC_PRIO_MASKING, > .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, > .matches = can_use_gic_priorities, > - .sys_reg = SYS_ID_AA64PFR0_EL1, > - .field_pos = ID_AA64PFR0_EL1_GIC_SHIFT, > - .field_width = 4, > - .sign = FTR_UNSIGNED, > - .min_field_value = 1, > }, > #endif > #ifdef CONFIG_ARM64_E0PD > -- > 2.30.2 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel