From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 67F83C05027 for ; Thu, 26 Jan 2023 10:25:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=5mxaqi96XXCDe39rW4XO+6RPrq/V47MaIGwjmWxh3A8=; b=e+RU7chqpEq+OG 4sLHqOo/njY0nwv+GVVX5iPrbufJ+PlzIUjvL9LldE50O3F4oKh95YJdLnKXCazPXDysOKTkmLArI XrlZ7wjaqycJmxVsqWa39VwUonh5OfLoEpwuWM2H80QAoV9w5AnxOvjggo6PLJhtJiNoBIOrp4hoG 0tdoAfiy0u5qS/HUVpmDjW9KhzQsPQp4oPMXXJ+z9WbLgqyLyIkD/oUdR3o3eN0cYRGuxGI5HeBdu iDU7y+zwnJBnhhat7XpEgh/Y4Ji+hLULZ2FlU/GhZozi6lyu8qywZtgFXymn1d285Od1h6968nBbC vtjzG/o6s/uRWZE3FX/g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pKzQt-00AQo9-6n; Thu, 26 Jan 2023 10:24:39 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pKzQp-00AQmz-QS for linux-arm-kernel@lists.infradead.org; Thu, 26 Jan 2023 10:24:37 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 06BE74B3; Thu, 26 Jan 2023 02:25:11 -0800 (PST) Received: from FVFF77S0Q05N (unknown [10.57.10.122]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3623C3F71E; Thu, 26 Jan 2023 02:24:28 -0800 (PST) Date: Thu, 26 Jan 2023 10:24:21 +0000 From: Mark Rutland To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, broonie@kernel.org, catalin.marinas@arm.com, will@kernel.org Subject: Re: [PATCH v2 4/5] arm64: add ARM64_HAS_GIC_PRIO_RELAXED_SYNC cpucap Message-ID: References: <20230125163826.496739-1-mark.rutland@arm.com> <20230125163826.496739-5-mark.rutland@arm.com> <878rhpely6.wl-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <878rhpely6.wl-maz@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230126_022435_939784_EA2B0CCF X-CRM114-Status: GOOD ( 20.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jan 26, 2023 at 08:31:29AM +0000, Marc Zyngier wrote: > On Wed, 25 Jan 2023 16:38:25 +0000, > Mark Rutland wrote: > > [...] > > > @@ -1768,16 +1759,8 @@ static void gic_enable_nmi_support(void) > > for (i = 0; i < gic_data.ppi_nr; i++) > > refcount_set(&ppi_nmi_refs[i], 0); > > > > - /* > > - * Linux itself doesn't use 1:N distribution, so has no need to > > - * set PMHE. The only reason to have it set is if EL3 requires it > > - * (and we can't change it). > > - */ > > I think this is still an important comment as it gives a rationale for > the extra synchronisation even if Linux doesn't use 1:N distribution: > If you get secure interrupts in the non-secure priority space, they > are subjected to the NS PMR setting. > > Could you find a new home for it? Sure; I'll add it verbatim to the end of the comment block when we detect the cpucap, i.e. | static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, | int scope) | { | /* | * If we're not using priority masking then we won't be poking PMR_EL1, | * and there's no need to relax synchronization of writes to it, and | * ICC_CTLR_EL1 might not be accessible and we must avoid reads from | * that. | * | * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU | * feature, so will be detected earlier. | */ | BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); | if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) | return false; | | /* | * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a | * hint for interrupt distribution, a DSB is not necessary when | * unmasking IRQs via PMR, and we can relax the barrier to a NOP. | * | * Linux itself doesn't use 1:N distribution, so has no need to | * set PMHE. The only reason to have it set is if EL3 requires it | * (and we can't change it). | */ | return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; | } Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel