From: Mark Rutland <mark.rutland@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org, broonie@kernel.org,
catalin.marinas@arm.com, will@kernel.org
Subject: Re: [PATCH v2 5/5] arm64: irqflags: use alternative branches for pseudo-NMI logic
Date: Thu, 26 Jan 2023 10:31:52 +0000 [thread overview]
Message-ID: <Y9JWmGyJerZK9STD@FVFF77S0Q05N> (raw)
In-Reply-To: <877cx9el3x.wl-maz@kernel.org>
On Thu, Jan 26, 2023 at 08:49:38AM +0000, Marc Zyngier wrote:
> On Wed, 25 Jan 2023 16:38:26 +0000,
> Mark Rutland <mark.rutland@arm.com> wrote:
>
> [...]
>
> > +static __always_inline void __daif_local_irq_restore(unsigned long flags)
> > +{
> > + barrier();
> > + write_sysreg(flags, daif);
> > + barrier();
> > +}
> > +
> > +static __always_inline void __pmr_local_irq_restore(unsigned long flags)
> > +{
> > + barrier();
> > + write_sysreg_s(flags, SYS_ICC_PMR_EL1);
> > + pmr_sync();
> > + barrier();
> > +}
>
> It would be good to at least mention why we need these compile-time
> barriers which are not that explicit in the existing code. I guess
> they are equivalent to the "memory" clobber in the asm sequences that
> this replaces,
Yes; that was the idea.
> but they don't seem to be used consistently throughout this patch.
Yes; looking with fresh eyes, the missing barriers around PMR manipulation are
buggy. Thanks for pointing that out!
I'll go and add the missing barriers, and update the commit message
accordingly.
I'll also use barrier() around the DAIF helpers rather than a memory clobber so
that the equivalent DAIF and PMR helpers more clearly correspond to one
another.
Thanks,
Mark.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-01-26 10:32 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-25 16:38 [PATCH v2 0/5] arm64: pseudo-nmi: elide code when CONFIG_ARM64_PSEUDO_NMI=n Mark Rutland
2023-01-25 16:38 ` [PATCH v2 1/5] arm64: rename ARM64_HAS_SYSREG_GIC_CPUIF to ARM64_HAS_GIC_CPUIF_SYSREGS Mark Rutland
2023-01-25 16:38 ` [PATCH v2 2/5] arm64: rename ARM64_HAS_IRQ_PRIO_MASKING to ARM64_HAS_GIC_PRIO_MASKING Mark Rutland
2023-01-25 16:38 ` [PATCH v2 3/5] arm64: make ARM64_HAS_GIC_PRIO_MASKING depend on ARM64_HAS_GIC_PRIO_MASKING Mark Rutland
2023-01-25 18:05 ` Alexandru Elisei
2023-01-25 18:27 ` Mark Rutland
2023-01-25 16:38 ` [PATCH v2 4/5] arm64: add ARM64_HAS_GIC_PRIO_RELAXED_SYNC cpucap Mark Rutland
2023-01-26 8:31 ` Marc Zyngier
2023-01-26 10:24 ` Mark Rutland
2023-01-25 16:38 ` [PATCH v2 5/5] arm64: irqflags: use alternative branches for pseudo-NMI logic Mark Rutland
2023-01-26 8:49 ` Marc Zyngier
2023-01-26 10:31 ` Mark Rutland [this message]
2023-01-26 8:51 ` [PATCH v2 0/5] arm64: pseudo-nmi: elide code when CONFIG_ARM64_PSEUDO_NMI=n Marc Zyngier
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Y9JWmGyJerZK9STD@FVFF77S0Q05N \
--to=mark.rutland@arm.com \
--cc=broonie@kernel.org \
--cc=catalin.marinas@arm.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=maz@kernel.org \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).