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Thu, 28 Jan 2021 11:24:39 +0000 Received: from hirez.programming.kicks-ass.net (hirez.programming.kicks-ass.net [192.168.1.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by noisy.programming.kicks-ass.net (Postfix) with ESMTPS id B704E3059C6; Thu, 28 Jan 2021 12:24:34 +0100 (CET) Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id EAC6A21A78F53; Thu, 28 Jan 2021 12:24:33 +0100 (CET) Date: Thu, 28 Jan 2021 12:24:33 +0100 From: Peter Zijlstra To: Alexander Sverdlin Subject: Re: [PATCH 1/2] qspinlock: Ensure writes are pushed out of core write buffer Message-ID: References: <20210127200109.16412-1-alexander.sverdlin@nokia.com> <20210127222158.GB848@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ingo Molnar , Will Deacon , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Russell King Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jan 28, 2021 at 08:36:24AM +0100, Alexander Sverdlin wrote: > >> diff --git a/kernel/locking/mcs_spinlock.h b/kernel/locking/mcs_spinlock.h > >> index 5e10153..10e497a 100644 > >> --- a/kernel/locking/mcs_spinlock.h > >> +++ b/kernel/locking/mcs_spinlock.h > >> @@ -89,6 +89,11 @@ void mcs_spin_lock(struct mcs_spinlock **lock, struct mcs_spinlock *node) > >> return; > >> } > >> WRITE_ONCE(prev->next, node); > >> + /* > >> + * This is necessary to make sure that the corresponding "while" in the > >> + * mcs_spin_unlock() doesn't loop forever > >> + */ > >> + smp_wmb(); > > If it loops forever, that's broken hardware design; store buffers need to > > drain. I don't think we should add unconditional barriers to bodge this. > > The comment is a bit exaggerating the situation, but it's undeterministic and you see the > measurements above. Something is wrong in the qspinlocks code, please consider this patch > "RFC", but something has to be done here. The qspinlock code has been TLA+ modelled and has had extensive memory ordering analysis. It has had lots of runtime on extremely large x86, arm64, and Power machines. I'm fairly confident there is nothing wrong. What I do think is more likely is that your platform is broken, it wouldn't be the first MIPS that's got store-buffers completely wrong, see commit: a30718868915 ("MIPS: Change definition of cpu_relax() for Loongson-3") Working around micro arch store-buffer issues is not something the generic code is for. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel