From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF835C433DB for ; Sun, 7 Feb 2021 16:43:37 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7350F60295 for ; Sun, 7 Feb 2021 16:43:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7350F60295 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=lunn.ch Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=HV8gtSbEc4ATrjdKwVZH1lMKPd/uF+a/V4xPuvxpTLc=; b=tkwa8r+gWmxFqD2S3Z1NK/zVO PxIgGCYzDghtZUnj0iiQGswGaBIxtQWtfu7Cl1WGtKRu1nNrCk8tn6cSbpoPVqKJq8hnZsAKJsPB+ IlXSfYPCD+2E5+uxB3ZLKJ1usPbZJkk6n1gKhI9t4A2dbYfsXTObCHvGh9ONKQgp9g/Q7yql/NC/c +AOn5P1FOFG5zxy6dm7j+Ie7PIwPQjGeUQsUdmHw7gcdVVPSB4wjaLRkDzUMNLGQIa3b0JlptVCzs cmRe4j1fXKUz1g2wB4rsrJ/xZj3K1CUYt8T9SRLwM2DOHDj4rh54bMWpqWzpayMigiYkiVTc2GCh+ 98cTLjXQw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l8n8F-0000ER-5y; Sun, 07 Feb 2021 16:41:55 +0000 Received: from vps0.lunn.ch ([185.16.172.187]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l8n8D-0000Dq-0A for linux-arm-kernel@lists.infradead.org; Sun, 07 Feb 2021 16:41:53 +0000 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1l8n7f-004ghT-5o; Sun, 07 Feb 2021 17:41:19 +0100 Date: Sun, 7 Feb 2021 17:41:19 +0100 From: Andrew Lunn To: stefanc@marvell.com Subject: Re: [RESEND PATCH v8 net-next 03/15] net: mvpp2: add CM3 SRAM memory map Message-ID: References: <1612685964-21890-1-git-send-email-stefanc@marvell.com> <1612685964-21890-4-git-send-email-stefanc@marvell.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1612685964-21890-4-git-send-email-stefanc@marvell.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210207_114153_092577_6FB73A64 X-CRM114-Status: GOOD ( 28.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, ymarkman@marvell.com, gregory.clement@bootlin.com, netdev@vger.kernel.org, atenart@kernel.org, linux-kernel@vger.kernel.org, linux@armlinux.org.uk, nadavh@marvell.com, rmk+kernel@armlinux.org.uk, robh+dt@kernel.org, thomas.petazzoni@bootlin.com, kuba@kernel.org, mw@semihalf.com, davem@davemloft.net, linux-arm-kernel@lists.infradead.org, sebastian.hesselbarth@gmail.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sun, Feb 07, 2021 at 10:19:12AM +0200, stefanc@marvell.com wrote: > From: Stefan Chulski > > This patch adds CM3 memory map and CM3 read/write callbacks. > No functionality changes. > > Signed-off-by: Stefan Chulski > --- > drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 7 +++ > drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 63 +++++++++++++++++++- > 2 files changed, 67 insertions(+), 3 deletions(-) > > diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h > index 6bd7e40..aec9179 100644 > --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h > +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h > @@ -748,6 +748,9 @@ > #define MVPP2_TX_FIFO_THRESHOLD(kb) \ > ((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) > > +/* MSS Flow control */ > +#define MSS_SRAM_SIZE 0x800 > + > /* RX buffer constants */ > #define MVPP2_SKB_SHINFO_SIZE \ > SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) > @@ -925,6 +928,7 @@ struct mvpp2 { > /* Shared registers' base addresses */ > void __iomem *lms_base; > void __iomem *iface_base; > + void __iomem *cm3_base; > > /* On PPv2.2, each "software thread" can access the base > * register through a separate address space, each 64 KB apart > @@ -996,6 +1000,9 @@ struct mvpp2 { > > /* page_pool allocator */ > struct page_pool *page_pool[MVPP2_PORT_MAX_RXQ]; > + > + /* CM3 SRAM pool */ > + struct gen_pool *sram_pool; > }; > > struct mvpp2_pcpu_stats { > diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c > index a07cf60..307f9fd 100644 > --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c > +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c > @@ -25,6 +25,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -6846,6 +6847,44 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) > return 0; > } > > +static int mvpp2_get_sram(struct platform_device *pdev, > + struct mvpp2 *priv) > +{ > + struct device_node *dn = pdev->dev.of_node; > + static bool defer_once; > + struct resource *res; > + > + if (has_acpi_companion(&pdev->dev)) { > + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); > + if (!res) { > + dev_warn(&pdev->dev, "ACPI is too old, Flow control not supported\n"); > + return 0; > + } > + priv->cm3_base = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(priv->cm3_base)) > + return PTR_ERR(priv->cm3_base); > + } else { > + priv->sram_pool = of_gen_pool_get(dn, "cm3-mem", 0); > + if (!priv->sram_pool) { > + if (!defer_once) { > + defer_once = true; > + /* Try defer once */ > + return -EPROBE_DEFER; > + } > + dev_warn(&pdev->dev, "DT is too old, Flow control not supported\n"); > + return -ENOMEM; > + } > + /* cm3_base allocated with offset zero into the SRAM since mapping size > + * is equal to requested size. > + */ > + priv->cm3_base = (void __iomem *)gen_pool_alloc(priv->sram_pool, > + MSS_SRAM_SIZE); > + if (!priv->cm3_base) > + return -ENOMEM; > + } For v2 i asked: > I'm wondering if using a pool even makes sense. The ACPI case just > ioremap() the memory region. Either this memory is dedicated, and > then there is no need to use a pool, or the memory is shared, and at > some point the ACPI code is going to run into problems when some > other driver also wants access. There was never an answer to this. Also, the defer_once stuff is odd. You don't see any other driver do this. The core decides when to give up probing a device. This is partially an API problem. of_gen_pool_get() gives you no idea why it failed. Is the property missing, or has the SRAM not probed yet. If the answer to my question is yes, a pool does make sense, it would be good to add an of_gen_pool_get_optional() which returns ERR_PTR(-EPROBE_DEFER) if the property is in DT, but is not yet available, NULL if the properties does not exist, and a pointer if everything goes well. Andrew _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel