From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37EDBC433E0 for ; Fri, 5 Mar 2021 07:55:32 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A394665004 for ; Fri, 5 Mar 2021 07:55:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A394665004 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=atomide.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=REYEVHb/bUhkkii9Kei10e3a0vkORShkjULdp87Z77s=; b=O7lrzCtvQhkaPsCc07RoB829B ZCR6h/Et8Ku/JBTZ23IuymxWW8CVIn8QTnGtpHkRV+oQCU6bSwQFTQfvCU5OT2cTEZrS/Y8aor/7m YNS2hJ1w54dAcYyMrFjNo920iAB1WQPeULx1XnAYsDxGixKk2heaAKaIT1DwQVJyseZzkN5zYUvmu ezVvN3i0I2AGHdHQthO3HpLqrG5n99diUMeBxejmHXEY45aiBXIQLi/PRK/u0T8X55w3+1xz/s3nR t+ihD4SHtRkPV12RQne3h/CnCotKSPHovw6ZgcpCwPXHeGGkM6UCCRlmgzerc4nrcmUXzjv7eKIJ5 v0xSPUhEQ==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lI5HL-00Dqfr-4S; Fri, 05 Mar 2021 07:53:43 +0000 Received: from muru.com ([72.249.23.125]) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lI5HH-00Dqep-J1 for linux-arm-kernel@lists.infradead.org; Fri, 05 Mar 2021 07:53:41 +0000 Received: from atomide.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id 701C380BA; Fri, 5 Mar 2021 07:54:17 +0000 (UTC) Date: Fri, 5 Mar 2021 09:53:35 +0200 From: Tony Lindgren To: Grygorii Strashko Cc: Daniel Lezcano , Thomas Gleixner , Keerthy , linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 1/3] clocksource/drivers/timer-ti-dm: Fix posted mode status check order Message-ID: References: <20210304072135.52712-1-tony@atomide.com> <20210304072135.52712-2-tony@atomide.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210305_075339_799540_453A9F6C X-CRM114-Status: GOOD ( 14.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org * Grygorii Strashko [210304 20:58]: > On 04/03/2021 09:21, Tony Lindgren wrote: > > When the timer is configured in posted mode, we need to check the write- > > posted status register (TWPS) before writing to the register. ... > > --- a/drivers/clocksource/timer-ti-dm-systimer.c > > +++ b/drivers/clocksource/timer-ti-dm-systimer.c > > @@ -449,13 +449,13 @@ static int dmtimer_set_next_event(unsigned long cycles, > > struct dmtimer_systimer *t = &clkevt->t; > > void __iomem *pend = t->base + t->pend; > > - writel_relaxed(0xffffffff - cycles, t->base + t->counter); > > while (readl_relaxed(pend) & WP_TCRR) > > cpu_relax(); > > + writel_relaxed(0xffffffff - cycles, t->base + t->counter); > > - writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl); > > while (readl_relaxed(pend) & WP_TCLR) > > cpu_relax(); > > + writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl); > > It seems static [and inline] helper here could be better solution. no? Well we wanted to get rid of the confusing macros. And in this case I suspect we can eventually do just one read of the pending register for the registers used mask rather than check the status separately multiple times. But that needs to be carefully tested and is not a fix :) Regards, Tony _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel