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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id s193sm625571oih.52.2021.03.11.08.31.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Mar 2021 08:31:18 -0800 (PST) Date: Thu, 11 Mar 2021 10:31:16 -0600 From: Bjorn Andersson To: Sai Prakash Ranjan Cc: Souradeep Chowdhury , Rob Herring , Andy Gross , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, sibis@codeaurora.org, Rajendra Nayak , vkoul@kernel.org Subject: Re: [PATCH V1 2/6] soc: qcom: dcc: Add driver support for Data Capture and Compare unit(DCC) Message-ID: References: <48556129a02c9f7cd0b31b2e8ee0f168e6d211b7.1615393454.git.schowdhu@codeaurora.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210311_163125_828117_454FEA06 X-CRM114-Status: GOOD ( 40.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu 11 Mar 00:19 CST 2021, Sai Prakash Ranjan wrote: > Hi Bjorn, > > On 2021-03-11 04:49, Bjorn Andersson wrote: > > On Wed 10 Mar 10:46 CST 2021, Souradeep Chowdhury wrote: > > > > > The DCC is a DMA Engine designed to capture and store data > > > during system crash or software triggers. The DCC operates > > > based on link list entries which provides it with data and > > > addresses and the function it needs to perform. These > > > functions are read, write and loop. Added the basic driver > > > in this patch which contains a probe method which instantiates > > > the resources needed by the driver. DCC has it's own SRAM which > > > needs to be instantiated at probe time as well. > > > > > > > So to summarize, the DCC will upon a crash copy the configured region > > into the dcc-ram, where it can be retrieved either by dumping the memory > > over USB or from sysfs on the next boot? > > > > Not just the next boot, but also for the current boot via /dev/dcc_sram, > more below. > Interesting! > > > Signed-off-by: Souradeep Chowdhury > > > --- > > > drivers/soc/qcom/Kconfig | 8 + > > > drivers/soc/qcom/Makefile | 1 + > > > drivers/soc/qcom/dcc.c | 388 > > > ++++++++++++++++++++++++++++++++++++++++++++++ > > > 3 files changed, 397 insertions(+) > > > create mode 100644 drivers/soc/qcom/dcc.c > > > > > ... > > > > > How about implementing this using pstore instead of exposing it through > > a custom /dev/dcc_sram (if I read the code correclty) > > > > Using pstore is definitely a good suggestion, we have been thinking of > adding it as a separate change once the basic support for DCC gets in. > But pstore ram backend again depends on warm reboot which is present only > in chrome compute platforms but android platforms do not officially support > warm reboot. Pstore with block devices as a backend would be ideal but it > is still a work in progress to use mmc as the backend [1]. > I was under the impression that we can have multiple pstore implementations active, so we would have ramoops and dcc presented side by side after such restart. Perhaps that's a misunderstanding on my part? > Now the other reason as to why we need this dev interface in addition to > pstore, > > * Pstore contents are retrieved on the next boot, but DCC SRAM contents > can be collected via dev interface for the current boot via SW trigger. > Lets say we have some non-fatal errors in one of the subsystems and we > want to analyze the register values, it becomes as simple as configuring > that region, trigger dcc and collect the sram contents and parse it. > > echo "addr" > /sys/bus/platform/devices/***.dcc/config > echo 1 > /sys/bus/platform/devices/***.dcc/trigger > cat /dev/dcc_sram > dcc_sram.bin > python dcc_parser.py -s dcc_sram.bin --v2 -o output/ > > We don't have to reboot at all for SW triggers. This is very useful and > widely used internally. > > Is the custom /dev/dcc_sram not recommended because of the dependency on > the userspace component being not available openly? If so, we already have > the dcc parser upstream which we use to extract the sram contents [2]. > My concern is that we come up with a custom chardev implementation for something that already exists or should exist in a more generic form. In the runtime sequence above, why don't you have trigger just generate a devcoredump? But perhaps the answer is that we want a unified interface between the restart and runtime use cases? It would be nice to have some more details of how I can use this and how to operate the sysfs interface to achieve that, would you be able to elaborate on this? Regards, Bjorn > [1] > https://lore.kernel.org/lkml/20210120121047.2601-1-bbudiredla@marvell.com/ > [2] https://source.codeaurora.org/quic/la/platform/vendor/qcom-opensource/tools/tree/dcc_parser > > Thanks, > Sai > > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel