From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1542DC433B4 for ; Fri, 30 Apr 2021 11:48:30 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C63AD61362 for ; Fri, 30 Apr 2021 11:48:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C63AD61362 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=jZqq/cOO05+XZUqtbM3kWIBoNry2K3UpjRVhCzEhazQ=; b=cYgWTWEFZAg0SpLBqTO0kmxjl kYoF8AIBF0NrOEHpgEX7VZmyRalerGZ9BwvBIFNBjEBfKj14e+iAGdyrd7ltLxAhXpSFAQrl5MBl/ WFnB8ofrTS44zZVt5GuGO/C0MfWLheI++qaXJXJMdIqaMaZicfk2wTm/CNBRtFH5sSLVkI/xuRAR1 b+nfAgNnAOLZJFjC3oXDLzI1UlEMmCiQfcXmWsYHSlsvNXXuSBhAUcLdivOm+n481MTjjHqEgieSo HW8zLUsAUwGNKp5ag4eG1L/j56WwnY9cmFiyrS+rxWvk7ZiEc+Gb7xQUs6luPsXk97uD0OM8O094O XafTq0PpQ==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lcRbb-007kSD-8w; Fri, 30 Apr 2021 11:46:47 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lcRbX-007kRx-KG for linux-arm-kernel@desiato.infradead.org; Fri, 30 Apr 2021 11:46:43 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=In-Reply-To:Content-Type:MIME-Version :References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=H46bKe9eoQRMLExgm9ShYxfb8kkQxbU8/uuDK5bE+Ck=; b=P7MMyDAPPN+oI6ZP3i4TmGkTjU hJirUw0Hfm+BJ1Te9UfehknEmJbBRf3qmer97m7MWJhyqCqKAS2Ska0lxVDgXjlSiz4bDdkKwHrKS 03nVim713AkmJXz3SBA767NKqzk1SO/rIvUaAY1dWQiDnxMtki/tfEdpPaGhqnhEthKxNl848aLbe 1b4/lM6i149KlK9ZJS4zPVSxrlLqKU13BJcHLz9bbbnsc/U8aik6bM9c8qihNh8Up+d/Q8kPnVNM1 1ACVRsWK9NjgTX8UVbjdzpHX10lRNMAQ+QeItocMqFMGRybj+lsgzYMWHUiSTct6BDrmk7Dv8eNtV QQs6aNFQ==; Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lcRbR-001L6N-Vz for linux-arm-kernel@lists.infradead.org; Fri, 30 Apr 2021 11:46:39 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id BDBDC613E8; Fri, 30 Apr 2021 11:46:35 +0000 (UTC) Date: Fri, 30 Apr 2021 12:46:32 +0100 From: Catalin Marinas To: "Luck, Tony" Cc: "Chatre, Reinette" , "tan.shaopeng@fujitsu.com" , "Yu, Fenghua" , "'linux-kernel@vger.kernel.org'" , "'linux-arm-kernel@lists.infradead.org'" , 'James Morse' , "misono.tomohiro@fujitsu.com" Subject: Re: About add an A64FX cache control function into resctrl Message-ID: References: <14ddf86b-89e1-ba26-b684-f3d5d5f8ade7@intel.com> <49cdd0b707194148915e2efe2ab5d707@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <49cdd0b707194148915e2efe2ab5d707@intel.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210430_044638_072170_1D4ABDAA X-CRM114-Status: GOOD ( 11.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Apr 29, 2021 at 05:50:20PM +0000, Luck, Tony wrote: > >>>> [Sector cache function] > >>>> The sector cache function split cache into multiple sectors and > >>>> control them separately. It is implemented on the L1D cache and > >>>> L2 cache in the A64FX processor and can be controlled individually > >>>> for L1D cache and L2 cache. A64FX has no L3 cache. Each L1D cache and > >>>> L2 cache has 4 sectors. Which L1D sector is used is specified by the > >>>> value of [57:56] bits of address, how many ways of sector are > >>>> specified by the value of register (IMP_SCCR_L1_EL0). > >>>> Which L2 sector is used is specified by the value of [56] bits of > >>>> address, and how many ways of sector are specified by value of > >>>> register (IMP_SCCR_ASSIGN_EL1, IMP_SCCR_SET0_L2_EL1, > >>>> IMP_SCCR_SET1_L2_EL1). > > Are A64FX binaries position independent? I.e. could the OS reassign > a running task to a different sector by remapping it to different virtual > addresses during a context switch? Arm64 supports a maximum of 52-bit of virtual or physical addresses. The maximum the MMU would produce would be a 52-bit output address. I presume bits 56, 57 of the address bus are used for some cache affinity (sector selection) but they don't influence the memory addressing, nor could the MMU set them. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel