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Peter Anvin" , Mathieu Poirier , Suzuki K Poulose , Mike Leach , Adrian Hunter , Andi Kleen , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 4/8] perf/x86: Add barrier after updating bts Message-ID: References: <20210602103007.184993-1-leo.yan@linaro.org> <20210602103007.184993-5-leo.yan@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210602103007.184993-5-leo.yan@linaro.org> X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jun 02, 2021 at 06:30:03PM +0800, Leo Yan wrote: > Add barrier wmb() to separate the AUX data store and aux_head store. > > Signed-off-by: Leo Yan > --- > arch/x86/events/intel/bts.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/x86/events/intel/bts.c b/arch/x86/events/intel/bts.c > index 6320d2cfd9d3..4a015d160bc5 100644 > --- a/arch/x86/events/intel/bts.c > +++ b/arch/x86/events/intel/bts.c > @@ -209,6 +209,9 @@ static void bts_update(struct bts_ctx *bts) > } else { > local_set(&buf->data_size, head); > } > + > + /* The WMB separates data store and aux_head store matches. */ > + wmb(); Alexander, do we indeed need an MFENCE here? or is the BTS hardware coherent, in which case a compiler barrier would be sufficient. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel