From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F915C47083 for ; Wed, 2 Jun 2021 09:27:42 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D6FDD613B4 for ; Wed, 2 Jun 2021 09:27:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D6FDD613B4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=atomide.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=m5Oc4JiNlPdkCof3epJJAkjTCLDsLj6woIkTX3dYu44=; b=o6O0TuKtnmCAZ1 nZ5tFCqaKPC+88WOfvrmlT/eWkOD8gm43mUP8PTenTHo/+DcZ4FoSD+7CQ14GO/uukBeGF4yVS054 VR9eDh94fUO8FSoKbrwbGsyMslO4Wq5AF0E4c3D9hhfJXQYOhr0lZhmIzQn7t3FIU3qoOHtCy6E79 adXAuFlBsaM3Uon7Y3uaC0REZZCLXUNFJgsitz8vf19QZUh7U5MCiD+2GqureWNfTpqSkZ4YDxjrU 1c0RhPhPH0Ekah7VAEjKfr4ASN6rW/mvwAvrtVhHKzlJsfuH1BtHk8k1jgFV91nWOkaUxgEXmpRtz O5uDwOveOXa25B1QOfRQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1loN8k-002wtr-Tz; Wed, 02 Jun 2021 09:26:19 +0000 Received: from muru.com ([72.249.23.125]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1loN8h-002wsd-N9 for linux-arm-kernel@lists.infradead.org; Wed, 02 Jun 2021 09:26:17 +0000 Received: from atomide.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id D2C858027; Wed, 2 Jun 2021 09:26:18 +0000 (UTC) Date: Wed, 2 Jun 2021 12:26:08 +0300 From: Tony Lindgren To: Sven Peter Cc: Rob Herring , devicetree@vger.kernel.org, linux-clk , linux-arm-kernel , "linux-kernel@vger.kernel.org" , Hector Martin , Michael Turquette , Stephen Boyd , Mark Kettenis , Arnd Bergmann Subject: Re: [PATCH 0/3] Apple M1 clock gate driver Message-ID: References: <20210524182745.22923-1-sven@svenpeter.dev> <9ff6ec26-4b78-4684-9c23-16d5cbfef857@www.fastmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <9ff6ec26-4b78-4684-9c23-16d5cbfef857@www.fastmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210602_022615_822651_804BD1EB X-CRM114-Status: GOOD ( 25.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org * Sven Peter [210530 11:09]: > Hi, > > On Wed, May 26, 2021, at 09:18, Tony Lindgren wrote: > > Hi, > > > > * Rob Herring [210525 18:09]: > > > I would do a single node per mmio region with the register offset (or > > > offset / 4) being the clock id. This can still support new SoCs easily > > > if you have a fallback compatible. If you want/need to get all the > > > clocks, just walk the DT 'clocks' properties and extract all the IDs. > > > > I mostly agree.. Except I'd also leave out the artificial clock ID and > > just use real register offsets from the clock controller base instead. > > Sure, I'll do that. > > > > > So a single clock controller node for each MMIO range, then set > > #clock=cells = <1>. Then the binding follows what we have for the > > interrupts-extended binding for example. > > > > If the clock controller optionally needs some data in the dts, > > that can be added to the clock controller node. Or it can be driver > > internal built-in data. If the data for dts can be described in a > > generic way, even better :) > > Now the big question is *how* to describe this additional data in the > dts. Essentially I need to specify that e.g. to enable clock 0x270 > I first need to enable the (internal) clocks 0x1c0 and then 0x220. > Are you aware of any generic way to describe this? I'm not even sure > how a sane non-generic way would look like when I just have a single > clock controller node. To me it seems you might be able to recycle the assigned-clocks and assigned-clock-parents etc properties in the clock controller node. Sure the assigned-clocks property will point to clocks in the clock controller itself, and will have tens of entries, but should work :) And sounds like you can generate that list with some script from the Apple dtb. Regards, Tony _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel