From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1214C636C9 for ; Mon, 19 Jul 2021 06:37:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9524761166 for ; Mon, 19 Jul 2021 06:37:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9524761166 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=os.amperecomputing.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=aQ1j3bWFqixFPYCYGd00d0/hA3FPLqyafwxaFSy5Pdk=; b=h15BejcActN9Dj RZF+tZigzTntsdFgF4OlhpM2muhPeGAFPkw/HCPI+VodCJKEap0UiHtTaMwYJgvlIJnsRr3/BaOWM OHYj+MzqT1loY0BHhK4ue6iiRLVXWYvo+uxQ6xKiIhgIV+iQd7QdX4K1ncrRQs9znIf+PVygMLOyP 8h44a8ZKyR/rvM+Wah6iPk9TAh8GwdtHZ1qReQO4pQvBOcx6ZaXHLlecQdoYTRqGPMrFGdqxcavt+ 3WGKQJ/wUOoLRkPykZo5KrzfbzvxObVdr99hBRGm4FNMInDQN4ItWk6cZxMsbtmgefUAXEYXCkqC6 oPrmCgAuxQe7ONfPQffg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m5MsT-008Ups-UA; Mon, 19 Jul 2021 06:35:46 +0000 Received: from mail-bn7nam10on2091.outbound.protection.outlook.com ([40.107.92.91] helo=NAM10-BN7-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m5MsO-008Uot-8f for linux-arm-kernel@lists.infradead.org; Mon, 19 Jul 2021 06:35:42 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=TvLjxQZf1M8hWZe1efeq+J2nQkVbcwhO+927SJ4CcHHfb7BPQz/x8BO9z1845+kbH1O7PEAUeVmJHFqpmovSZNCxomfNWj129k67KNxz3MOn1AdORxp4Zeq1hPIayWlAxs4f9BHjQ7cxP4tiNPMGCy2hwzt33vf13SJGOeaFgqiOzixQxrkuLnl8rdl4FPy4+VOk7CB5EnBnedZcWQ5nwkYKie4OSq02MDznys54ECMfODjb0k0Pm2YHSfBARL0KXN8wNoMtc464cQu9dvVN+CTBYFQHJ6PnSRy4dE7u4YRohj2iQ5w3SEVA/e24dCx7qii0fEfLzRdGi8Snw6juIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bj5yBQv1ErHGS1SCRG3lshn+ymFEKa4vQ69lvBxmfh0=; b=DSTKoVx1EUx6dU3tNAGueMUxyPNhtwz+CpJI+/R/LV/DfqX6CMoJR7E8qM+GHvwM1CzHf2l15l9MjNxlzfpJ6ikE9mhP9EO8iWGCGAD+THCVSLDIKkVzNYsmregoulGtYF1dC1JEaQMOW7jzLJXor4NmskN3axsxsLWfzXHpkG/aFlMCuCZ6SXY4i5b6INJv0nvKyQdwt76qYaWxnncBY0mEUcSbcQ5yoAqC7sfzKXkrQ+qfMZhwAsQtMURkR5bRgsylA/hx8RSSJeUrwI9ftguKdTLuYMTGnnL1ZxllHJXKWX+gWAefwZGpQwhC9F6v0JRcGhsn7a+t91/mf8ISPA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=os.amperecomputing.com; dmarc=pass action=none header.from=os.amperecomputing.com; dkim=pass header.d=os.amperecomputing.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=os.amperecomputing.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bj5yBQv1ErHGS1SCRG3lshn+ymFEKa4vQ69lvBxmfh0=; b=viboEIKNkdtX7hZBHkc9/7+VDjY1inZ9quEpabGhyBbNcrRK9gbjnsVB8Gv7ALIuzhsDQgSdAYKjBBNoUwTtmh0fTncY2qN7Fev6HX548QJXOtUSIJ2bqdF728av2LHAn97oShGZmi1AZT1O0jiSSUoUvDNqS204rBJeTeMAhVo= Authentication-Results: linaro.org; dkim=none (message not signed) header.d=none;linaro.org; dmarc=none action=none header.from=os.amperecomputing.com; Received: from MWHPR0101MB3165.prod.exchangelabs.com (10.174.167.147) by CO1PR01MB6550.prod.exchangelabs.com (13.101.100.49) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.21; Mon, 19 Jul 2021 06:35:35 +0000 Received: from MWHPR0101MB3165.prod.exchangelabs.com ([fe80::9d11:11d3:b589:400a]) by MWHPR0101MB3165.prod.exchangelabs.com ([fe80::9d11:11d3:b589:400a%7]) with mapi id 15.20.4331.031; Mon, 19 Jul 2021 06:35:35 +0000 Date: Mon, 19 Jul 2021 14:35:24 +0800 From: Huang Shijie To: Sumit Garg Cc: linux-arm-kernel@lists.infradead.org Subject: Re: Fwd: [PATCH v5] arm64: Enable perf events based hard lockup detector Message-ID: References: <1610712101-14929-1-git-send-email-sumit.garg@linaro.org> Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: CY4PR22CA0075.namprd22.prod.outlook.com (2603:10b6:903:ad::13) To MWHPR0101MB3165.prod.exchangelabs.com (2603:10b6:301:2f::19) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from hsj-NUC11PAHi7 (180.167.209.74) by CY4PR22CA0075.namprd22.prod.outlook.com (2603:10b6:903:ad::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.21 via Frontend Transport; Mon, 19 Jul 2021 06:35:32 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2a68d1ce-3c1f-492e-a49c-08d94a7f69bb X-MS-TrafficTypeDiagnostic: CO1PR01MB6550: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hEMG/ofSeHPF73cPiB7GGKv1z3rAv+qjChd1pX+rL2vqWvWGulM0LqaxctGAXgx9D+f1Bw7nw8bz+dshAtTxCXF+HZ3eX+awiJoRmr05QV1+VZsZ9wnYSLBIzMulFzT3AEIbepF+HUFYexwurIi+5LBS6IopFlxf8I8MvbTkEKgh9bM7FcAbktZfUjuza3ziIzFtr8jlD3ZF5TnQ6bFT92wLdYF4Ss3rl+eL4Ms0V9T1JYT7V9b64AD8sh7CMJhwjrAZc0E7oxFJftxdsMsLwtWpn1Ae36/KkvQOqgX5RRIXr5ic7LqGseNs0aBn+M8fJMeuMlmR1GDUl/+rFiizbFjwnIwUkyc5bePXqP5aJZl/vJjH8/oxd2DK6XPNAVLvnurMkDq9WwJ3IZuF0pO8GnpjmgFJDOwaVVOmmOQO20CKuGeZYN3yPfJ7TmwCT+TKzpFPyzsjS/D5eUOoU1ykAtkEbirYDVwZCY5dZdvmtGGfbpsW6yqmfmdu8uevzkbAdc3XFr3mwbg47eBA8rq3u0eBVU262bv242v2/tps9guw1quuNFW4lGdT6wLX1MBX4zRyOeETm9lFXahD0aM45gI81ZfoBZ5LnwX5zzzsxBmHRE9RovRmBzklIbegVc7qMAiUI4ofz8xmzIhuZWVycHq5sqV6JaTmj1MI1liu6AjjDdTdfYoQ+IOb7ewp36zFnA2ryigyndFXjPjMnimBP7BdkNlhAixoLJgdbJRwoEtfPbxN14TlhTYdgn/QDQID4DvyZCKCEbsaPGHzxQyhnuTlgjrODkXyArhI512hRqg= X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:MWHPR0101MB3165.prod.exchangelabs.com; PTR:; CAT:NONE; SFS:(4636009)(396003)(346002)(39840400004)(136003)(376002)(366004)(33716001)(5660300002)(66476007)(66556008)(66946007)(38350700002)(38100700002)(6496006)(478600001)(8676002)(956004)(316002)(966005)(8936002)(9686003)(86362001)(186003)(52116002)(26005)(2906002)(6666004)(55016002)(83380400001)(6916009)(4326008); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?K4b/3p2AUFxzqipvDa0Dk6P4VKVPTDmy2GQsSJLa1qFFOnUIjEU8VjIwk3yw?= =?us-ascii?Q?1M4aKii8w3LDy5T8MFX1f8Im+bwsmK9TUpadUUgUsqyt5NhJ6Vo3HyEKIsuS?= =?us-ascii?Q?ZYZKxAroYLnwTYsxjF14Zz0dVIuK8eANLq0t//BZ9DtLVbWovYo+PWt9gfHK?= =?us-ascii?Q?LFBpBhGh1pHp6Dst2aLM9jm1BKWxUNu7CRRwgbNRIsFI3TTBDqWvmeH/0JSv?= =?us-ascii?Q?FHC66NwoZDC8DpF25lpC8jcEf1+eG94f1oHJVuiquO+Sr+Zbhz8GQo6lja6c?= =?us-ascii?Q?xGvSCbkZQie78e2Dv/efHFgAc6xLKM2xsTOi59H0W/vR3TW+5H4vGbpRPzjB?= =?us-ascii?Q?bqa+17i/H/0jul6+lS2mNDMnSNmQFHUypKMCNq/mf00/juND6x+RtOg3WA20?= =?us-ascii?Q?z66bTh+LWtk/USm93B81fKfyy1zMLUT5Y0w3BD546ix2MUCnZEyeDadwqaMj?= =?us-ascii?Q?XlAWHZlu+KISO5E0S78sjTqVsz58/0594BDF6YhV6Y4gPQhxZdkXFUWR3qdM?= =?us-ascii?Q?lLMQy1IAUs+OB41aaQsvRMkasD67W2831z6RVxMi+9NRP//0Ihdbs+oICeng?= =?us-ascii?Q?FiMrN46YoZ9Np0ttXTUkuq9ItRP5z9F9UaEmRAwwtCyjqLpPQCpsE3EjeKmb?= =?us-ascii?Q?F4LUrkXpquOjwHAATipNeZ14/9Q5J04zJq85U+NuyeWmMfqpILHWyRpmQFwj?= =?us-ascii?Q?qCgXiex/bp7nrXCFyiBt+d316w67mxwza+IGPByQj3Q927ZxzqYonsmQO6IN?= =?us-ascii?Q?I0SBu9/6QoKy88vunvjmxUYGcUZhYdDz/pISk4XnZumK4whLMdQp0od/tMKK?= =?us-ascii?Q?HKJXEyGwEv1EW3XKz3S/hgYUpYJew+QifwAvKVjgc5XlJUpgClTNFB1SgVE6?= =?us-ascii?Q?DJbeYWQ1WpgmU2DNRETvi+XBHsYTVGUs8pV9k0uFXREYxhcy1Jc2F5rvAetx?= =?us-ascii?Q?2nxkI4U3gzGLiiKkNB3Vgozs9WAohbe0O2mGHmdVpQ4xZ+l+yHioDY0e3eTh?= =?us-ascii?Q?mueYB78tWQN13c4RFf1c62+lqFaVLW6aylcgaPPQ+y53XVdsvAt0Gaif2QBB?= =?us-ascii?Q?RXKhb7zBdR+Cg5LaWx4v/qft3sRtcAw0et7V5DHkmDFMEC5jmU5tDf5S6eqj?= =?us-ascii?Q?/OsaF7jmw72q9c77BOf8Q+QWMlYxspTR+k7Y0ALG3iS+6o/3URBlzSyRwL4y?= =?us-ascii?Q?tdfDEsDG2pXP3SPe1JT+emj0bAD5gJuyn5TMXbZEoBdZgTsZzGMOonnyKZQq?= =?us-ascii?Q?8gpu67gVm6oCSKtY5rG+bwM9Z86Oegpuf10zmu1pH3v7nyNbqyKJkxXn1Gj4?= =?us-ascii?Q?k73M3B/zSMDxs4sKfM+4+yKm?= X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2a68d1ce-3c1f-492e-a49c-08d94a7f69bb X-MS-Exchange-CrossTenant-AuthSource: MWHPR0101MB3165.prod.exchangelabs.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jul 2021 06:35:35.0739 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 32XZEbItIfMavYV664TcPo+UgbbQRyi/sfpkN935DvcueOvTOb44h/9eV50vUVi75+tBuGpGUNcdYTWhC/qqNPSrWKWLIXjShcOP5nvYFSszKEz7yQJfn0f+XwEQ7e5u X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO1PR01MB6550 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210718_233540_447306_C6445C16 X-CRM114-Status: GOOD ( 35.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jul 19, 2021 at 11:48:33AM +0530, Sumit Garg wrote: > Subject: [PATCH v5] arm64: Enable perf events based hard lockup detector > To: , , > Cc: , , > , , > , , > , Sumit Garg > > > With the recent feature added to enable perf events to use pseudo NMIs > as interrupts on platforms which support GICv3 or later, its now been > possible to enable hard lockup detector (or NMI watchdog) on arm64 > platforms. So enable corresponding support. > > One thing to note here is that normally lockup detector is initialized > just after the early initcalls but PMU on arm64 comes up much later as > device_initcall(). So we need to re-initialize lockup detection once > PMU has been initialized. > > Signed-off-by: Sumit Garg > --- > > Changes in v5: > - Fix lockup_detector_init() invocation to be rather invoked from CPU > binded context as it makes heavy use of per-cpu variables and shouldn't > be invoked from preemptible context. > > Changes in v4: > - Rebased to latest pmu v7 NMI patch-set [1] and in turn use "has_nmi" > hook to know if PMU IRQ has been requested as an NMI. > - Add check for return value prior to initializing hard-lockup detector. > > [1] https://lkml.org/lkml/2020/9/24/458 > > Changes in v3: > - Rebased to latest pmu NMI patch-set [1]. > - Addressed misc. comments from Stephen. > > [1] https://lkml.org/lkml/2020/8/19/671 > > Changes since RFC: > - Rebased on top of Alex's WIP-pmu-nmi branch. > - Add comment for safe max. CPU frequency. > - Misc. cleanup. > > arch/arm64/Kconfig | 2 ++ > arch/arm64/kernel/perf_event.c | 48 ++++++++++++++++++++++++++++++++++++++++-- > drivers/perf/arm_pmu.c | 5 +++++ > include/linux/perf/arm_pmu.h | 2 ++ > 4 files changed, 55 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index f39568b..05e1735 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -174,6 +174,8 @@ config ARM64 > select HAVE_NMI > select HAVE_PATA_PLATFORM > select HAVE_PERF_EVENTS > + select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI && HW_PERF_EVENTS > + select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && > HAVE_PERF_EVENTS_NMI > select HAVE_PERF_REGS > select HAVE_PERF_USER_STACK_DUMP > select HAVE_REGS_AND_STACK_ACCESS_API > diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c > index 3605f77a..bafb7c8 100644 > --- a/arch/arm64/kernel/perf_event.c > +++ b/arch/arm64/kernel/perf_event.c > @@ -23,6 +23,8 @@ > #include > #include > #include > +#include > +#include > > /* ARMv8 Cortex-A53 specific event types. */ > #define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2 > @@ -1246,12 +1248,30 @@ static struct platform_driver armv8_pmu_driver = { > .probe = armv8_pmu_device_probe, > }; > > +static int __init lockup_detector_init_fn(void *data) > +{ > + lockup_detector_init(); > + return 0; > +} > + > static int __init armv8_pmu_driver_init(void) > { > + int ret; > + > if (acpi_disabled) > - return platform_driver_register(&armv8_pmu_driver); > + ret = platform_driver_register(&armv8_pmu_driver); > else > - return arm_pmu_acpi_probe(armv8_pmuv3_init); > + ret = arm_pmu_acpi_probe(armv8_pmuv3_init); > + > + /* > + * Try to re-initialize lockup detector after PMU init in > + * case PMU events are triggered via NMIs. > + */ > + if (ret == 0 && arm_pmu_irq_is_nmi()) > + smp_call_on_cpu(raw_smp_processor_id(), lockup_detector_init_fn, > + NULL, false); > + > + return ret; > } > device_initcall(armv8_pmu_driver_init) > > @@ -1309,3 +1329,27 @@ void arch_perf_update_userpage(struct perf_event *event, > userpg->cap_user_time_zero = 1; > userpg->cap_user_time_short = 1; > } > + > +#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF > +/* > + * Safe maximum CPU frequency in case a particular platform doesn't implement > + * cpufreq driver. Although, architecture doesn't put any restrictions on > + * maximum frequency but 5 GHz seems to be safe maximum given the available > + * Arm CPUs in the market which are clocked much less than 5 GHz. On the other > + * hand, we can't make it much higher as it would lead to a large hard-lockup > + * detection timeout on parts which are running slower (eg. 1GHz on > + * Developerbox) and doesn't possess a cpufreq driver. > + */ > +#define SAFE_MAX_CPU_FREQ 5000000000UL // 5 GHz > +u64 hw_nmi_get_sample_period(int watchdog_thresh) > +{ > + unsigned int cpu = smp_processor_id(); > + unsigned long max_cpu_freq; > + > + max_cpu_freq = cpufreq_get_hw_max_freq(cpu) * 1000UL; > + if (!max_cpu_freq) > + max_cpu_freq = SAFE_MAX_CPU_FREQ; > + > + return (u64)max_cpu_freq * watchdog_thresh; > +} > +#endif > diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c > index cb2f55f..794a37d 100644 > --- a/drivers/perf/arm_pmu.c > +++ b/drivers/perf/arm_pmu.c > @@ -726,6 +726,11 @@ static int armpmu_get_cpu_irq(struct arm_pmu *pmu, int cpu) > return per_cpu(hw_events->irq, cpu); > } > > +bool arm_pmu_irq_is_nmi(void) > +{ > + return has_nmi; > +} > + > /* > * PMU hardware loses all context when a CPU goes offline. > * When a CPU is hotplugged back in, since some hardware registers are > diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h > index 5054802..bf79667 100644 > --- a/include/linux/perf/arm_pmu.h > +++ b/include/linux/perf/arm_pmu.h > @@ -163,6 +163,8 @@ int arm_pmu_acpi_probe(armpmu_init_fn init_fn); > static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; } > #endif > > +bool arm_pmu_irq_is_nmi(void); > + > /* Internal functions only for core arm_pmu code */ > struct arm_pmu *armpmu_alloc(void); > struct arm_pmu *armpmu_alloc_atomic(void); > -- > 2.7.4 Tested-by: Huang Shijie _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel