From: Abel Vesa <abel.vesa@nxp.com>
To: Lucas Stach <l.stach@pengutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
NXP Linux Team <linux-imx@nxp.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
kernel@pengutronix.de, patchwork-lst@pengutronix.de
Subject: Re: [PATCH 1/2] clk: imx8mm: use correct mux type for clkout path
Date: Mon, 19 Jul 2021 13:36:38 +0300 [thread overview]
Message-ID: <YPVVtuj1imTTnwo9@ryzen> (raw)
In-Reply-To: <20210628211554.2510238-1-l.stach@pengutronix.de>
On 21-06-28 23:15:53, Lucas Stach wrote:
> The mux in the clkout path needs the current selected parent to
> be enabled for the the switch to work. Use the correct mux type
> to have the clk framework take care of this requirement.
>
> Fixes: c1ae5c6f789a ("clk: imx8mm: add clkout1/2 support")
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
I'm OK with this.
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
> ---
> drivers/clk/imx/clk-imx8mm.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
> index f1919fafb124..ce7127ccddab 100644
> --- a/drivers/clk/imx/clk-imx8mm.c
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -407,10 +407,10 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
> hws[IMX8MM_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
> hws[IMX8MM_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
>
> - hws[IMX8MM_CLK_CLKOUT1_SEL] = imx_clk_hw_mux("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
> + hws[IMX8MM_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
> hws[IMX8MM_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4);
> hws[IMX8MM_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
> - hws[IMX8MM_CLK_CLKOUT2_SEL] = imx_clk_hw_mux("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
> + hws[IMX8MM_CLK_CLKOUT2_SEL] = imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
> hws[IMX8MM_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4);
> hws[IMX8MM_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
>
> --
> 2.30.2
>
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next prev parent reply other threads:[~2021-07-19 10:39 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-28 21:15 [PATCH 1/2] clk: imx8mm: use correct mux type for clkout path Lucas Stach
2021-06-28 21:15 ` [PATCH 2/2] clk: imx8mn: " Lucas Stach
2021-07-19 10:37 ` Abel Vesa
2021-07-19 10:36 ` Abel Vesa [this message]
2021-07-29 10:45 ` [PATCH 1/2] clk: imx8mm: " Abel Vesa
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