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Received: from shell.armlinux.org.uk ([fd8f:7570:feb6:1:5054:ff:fe00:4ec]:45018) by pandora.armlinux.org.uk with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mOM6t-0006iP-WB; Thu, 09 Sep 2021 16:37:06 +0100 Received: from linux by shell.armlinux.org.uk with local (Exim 4.94.2) (envelope-from ) id 1mOM6p-0006P9-2l; Thu, 09 Sep 2021 16:37:03 +0100 Date: Thu, 9 Sep 2021 16:37:03 +0100 From: "Russell King (Oracle)" To: Geert Uytterhoeven Cc: Marc Zyngier , Linux ARM , Linux Kernel Mailing List , Will Deacon , Catalin Marinas , Thomas Gleixner , Jason Cooper , Sumit Garg , Valentin Schneider , Florian Fainelli , Gregory Clement , Andrew Lunn , Android Kernel Team , stable , Magnus Damm , Niklas =?iso-8859-1?Q?S=F6derlund?= , Linux-Renesas Subject: Re: [PATCH v2 07/17] irqchip/gic: Atomically update affinity Message-ID: References: <20200624195811.435857-1-maz@kernel.org> <20200624195811.435857-8-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210909_083915_803668_27363A62 X-CRM114-Status: GOOD ( 19.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Sep 09, 2021 at 05:22:01PM +0200, Geert Uytterhoeven wrote: > Despite the ARM Generic Interrupt Controller Architecture Specification > (both version 1.0 and 2.0) stating that the Interrupt Processor Targets > Registers are byte-accessible, the EMMA Mobile EV2 User's Manual > states that the interrupt registers can be accessed via the APB bus, > in 32-bit units. Using byte accesses locks up the system. Fun. Seems someone can't read ARMs documentation. Even the old ARM IHI 0048B.b document I have for the GIC from 2013 states "In addition, the GICD_IPRIORITYRn, GICD_ITARGETSRn, GICD_CPENDSGIRn, and GICD_SPENDSGIRn registers support byte accesses." However, this kind of thing is sadly not uncommon. There's been a similar issue with the PL011 UART driver as well - some platforms require 16-bit accesses instead of normal 32-bit accesses. > Unfortunately I only have remote access to the board showing the > issue. I did check that adding the writeb_relaxed() before the > writel_relaxed() that was used before also causes a lock-up, so the > issue is not an endian mismatch. > Looking at the driver history, these registers have always been > accessed using 32-bit accesses before. As byte accesses lead > indeed to simpler code, I'm wondering if they had been tried before, > and caused issues before? > > Since you said the locking was bogus before, due to the reliance on > the BL_SWITCHER option, I'm not suggesting a plain revert, but I'm > wondering what kind of locking you suggest to use instead? If byte accesses are not going to be workable, then the only answer _is_ a read-modify-write with working locking. -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last! _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel