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Sat, 25 Sep 2021 08:40:04 -0700 (PDT) Received: from piliu.users.ipa.redhat.com ([209.132.188.80]) by smtp.gmail.com with ESMTPSA id m1sm10633861pfc.183.2021.09.25.08.39.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Sep 2021 08:40:03 -0700 (PDT) Date: Sat, 25 Sep 2021 23:39:55 +0800 From: Pingfan Liu To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Sami Tolvanen , Julien Thierry , Thomas Gleixner , Yuichi Ito , linux-kernel@vger.kernel.org Subject: Re: [PATCHv2 1/5] arm64/entry-common: push the judgement of nmi ahead Message-ID: References: <20210924132837.45994-1-kernelfans@gmail.com> <20210924132837.45994-2-kernelfans@gmail.com> <20210924175306.GB42068@C02TD0UTHF1T.local> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210924175306.GB42068@C02TD0UTHF1T.local> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210925_084004_971712_C25242BA X-CRM114-Status: GOOD ( 22.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Sep 24, 2021 at 06:53:06PM +0100, Mark Rutland wrote: > On Fri, Sep 24, 2021 at 09:28:33PM +0800, Pingfan Liu wrote: > > In enter_el1_irq_or_nmi(), it can be the case which NMI interrupts an > > irq, which makes the condition !interrupts_enabled(regs) fail to detect > > the NMI. This will cause a mistaken account for irq. > Sorry about the confusing word "account", it should be "lockdep/rcu/.." > Can you please explain this in more detail? It's not clear which > specific case you mean when you say "NMI interrupts an irq", as that > could mean a number of distinct scenarios. > > AFAICT, if we're in an IRQ handler (with NMIs unmasked), and an NMI > causes a new exception we'll do the right thing. So either I'm missing a > subtlety or you're describing a different scenario.. > > Note that the entry code is only trying to distinguish between: > > a) This exception is *definitely* an NMI (because regular interrupts > were masked). > > b) This exception is *either* and IRQ or an NMI (and this *cannot* be > distinguished until we acknowledge the interrupt), so we treat it as > an IRQ for now. > b) is the aim. At the entry, enter_el1_irq_or_nmi() -> enter_from_kernel_mode()->rcu_irq_enter()/rcu_irq_enter_check_tick() etc. While at irqchip level, gic_handle_irq()->gic_handle_nmi()->nmi_enter(), which does not call rcu_irq_enter_check_tick(). So it is not proper to "treat it as an IRQ for now" > ... and we leave it to the irqchip to handle the gory details. We only The detail should hide in irqchip to decide if an exception is either NMI or IRQ. But could irqchip export the interface to entry? (This patch export two: handle_arch_nmi() and interrupt_is_nmi() ). Thanks, Pingfan _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel