From: Andrew Lunn <andrew@lunn.ch>
To: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: gregory.clement@bootlin.com, sebastian.hesselbarth@gmail.com,
robh+dt@kernel.org, kostap@marvell.com,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] arm/arm64: dts: Add MV88E6393X to CN9130-CRB device tree
Date: Fri, 8 Oct 2021 01:51:43 +0200 [thread overview]
Message-ID: <YV+IDzEdYuy+s/Ak@lunn.ch> (raw)
In-Reply-To: <20211007230619.957016-3-chris.packham@alliedtelesis.co.nz>
On Fri, Oct 08, 2021 at 12:06:19PM +1300, Chris Packham wrote:
> The CN9130-CRB boards have a MV88E6393X switch connected to eth0. Add
> the necessary dts nodes and properties for this.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> ---
>
> This is taken from the Marvell SDK. I've re-ordered the port entries to
> be in ascending order.
>
> arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 125 ++++++++++++++++++++
> 1 file changed, 125 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
> index e7918f325646..171f7394948e 100644
> --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
> +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
> @@ -185,6 +185,131 @@ &cp0_mdio {
> phy0: ethernet-phy@0 {
> reg = <0>;
> };
> +
> + switch6: switch0@6 {
> + /* Actual device is MV88E6393X */
> + compatible = "marvell,mv88e6190";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <6>;
Is the interrupt output connected to a GPIO?
> +
> + dsa,member = <0 0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + label = "notused-port0";
> + phy-mode = "10gbase-kr";
> + status = "disabled";
What is meant by not used? Does it go to a header? Is it not wired at
all? You don't need to list a port if it is not actually used. So
maybe you just want to delete this port all together?
> +
> + };
> +
> + port@1 {
> + reg = <1>;
> + label = "wan1";
> + phy-handle = <&switch0phy1>;
> + };
> +
> +
> + port@8 {
> + reg = <8>;
> + label = "lan8";
> + phy-handle = <&switch0phy8>;
> + };
> +
> + port@9 {
> + reg = <9>;
> + label = "wanp9";
Do these names correspond to some labeling? Ether the case or the silk
screen? wanp9 is an odd name. Is it connected to a header?
> + phy-mode = "10gbase-kr";
> + fixed-link {
> + speed = <10000>;
> + full-duplex;
> + };
> + };
Andrew
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next prev parent reply other threads:[~2021-10-07 23:53 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-07 23:06 [PATCH 0/2] arm/arm64: dts: Enable more network hardware Chris Packham
2021-10-07 23:06 ` [PATCH 1/2] arm/arm64: dts: Enable 2.5G Ethernet port on CN9130-CRB Chris Packham
2021-10-07 23:45 ` Andrew Lunn
2021-10-13 14:52 ` Gregory CLEMENT
2021-10-17 22:15 ` Chris Packham
2021-11-09 1:00 ` Chris Packham
2021-10-07 23:06 ` [PATCH 2/2] arm/arm64: dts: Add MV88E6393X to CN9130-CRB device tree Chris Packham
2021-10-07 23:51 ` Andrew Lunn [this message]
2021-10-08 0:09 ` Chris Packham
2021-10-10 14:45 ` Andrew Lunn
2021-10-10 15:21 ` Andrew Lunn
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