From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD671C433F5 for ; Tue, 5 Oct 2021 16:47:59 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7D0FF611C1 for ; Tue, 5 Oct 2021 16:47:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 7D0FF611C1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2I0dk06gZUkUrqazM6zIZRy9IOSJ0VyMulfcBQe/v7c=; b=u6ue2H4gZbL8zl QIBqFU4F9kKNa8juIQqO+9VN4yZuuKN+fMoCFd2RDMxakrny2AFMscCMdnp+gVjkgbkhVYsAwlCJg 5k6shSZOJ0YWCYEp7sBEhOOzom5485evGbE6lAH1XsfLC3vzWO46Rznk2+o0rm/YmZpY0S4eXNF8H gyDZKqxN5WlRp5C1Pm5RYB9gmObll4SBgwH5nyLvX9X1uxoWquZ9WyiRMywuRSENv4LIc4Oh1rLr4 v5wRs7TopVjTDU1ve3lqoMsFYtccIYUL2najiUuGxAp/a1K76s91EwKHIdaLZQocXlnlTx2JeNMG7 n2dBU+SSnf1afd7mmvNg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mXna5-00BJ8S-Vq; Tue, 05 Oct 2021 16:46:18 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mXna2-00BJ7U-5q for linux-arm-kernel@lists.infradead.org; Tue, 05 Oct 2021 16:46:15 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 6B46B611C5; Tue, 5 Oct 2021 16:46:12 +0000 (UTC) Date: Tue, 5 Oct 2021 17:46:09 +0100 From: Catalin Marinas To: Peter Collingbourne Cc: Vincenzo Frascino , Will Deacon , Andrey Konovalov , Evgenii Stepanov , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH] arm64: mte: avoid clearing PSTATE.TCO on entry unless necessary Message-ID: References: <20210929194525.3252555-1-pcc@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210929194525.3252555-1-pcc@google.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211005_094614_255114_94D0DCF5 X-CRM114-Status: GOOD ( 17.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Sep 29, 2021 at 12:45:24PM -0700, Peter Collingbourne wrote: > diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S > index 2f69ae43941d..85ead6bbb38e 100644 > --- a/arch/arm64/kernel/entry.S > +++ b/arch/arm64/kernel/entry.S > @@ -269,7 +269,28 @@ alternative_else_nop_endif > .else > add x21, sp, #PT_REGS_SIZE > get_current_task tsk > + ldr x0, [tsk, THREAD_SCTLR_USER] > .endif /* \el == 0 */ > + > + /* > + * Re-enable tag checking (TCO set on exception entry). This is only > + * necessary if MTE is enabled in either the kernel or the userspace > + * task in synchronous mode. With MTE disabled in the kernel and > + * disabled or asynchronous in userspace, tag check faults (including in > + * uaccesses) are not reported, therefore there is no need to re-enable > + * checking. This is beneficial on microarchitectures where re-enabling > + * TCO is expensive. > + */ > +#ifdef CONFIG_ARM64_MTE > +alternative_cb kasan_hw_tags_enable > + tbz x0, #SCTLR_EL1_TCF0_SHIFT, 1f > +alternative_cb_end > +alternative_if ARM64_MTE > + SET_PSTATE_TCO(0) > +alternative_else_nop_endif > +1: > +#endif I think we can get here from an interrupt as well. Can we guarantee that the sctlr_user is valid? We are not always in a user process context. Maybe only do the above checks if \el == 0, otherwise just bracket it with kasan_hw_tags_enable. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel