From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B06AC433F5 for ; Fri, 8 Oct 2021 08:47:05 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 373E060E74 for ; Fri, 8 Oct 2021 08:47:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 373E060E74 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=lHCJftIt1bbNTkPOFBFbFqFLXtYxMVoCbyMtwyL9t8I=; b=q6LuirKauJYhcs +Gsh08mkCyYn/jeforw+jB3bPHJPsj2jOqQ4W1IPJX1SsrB6NBnPDL0f2We7a+Qw0AwHQm9yhOHzz +AKmmYhkE1rKjPly0gvFakE/3Pu7Pf9jf77xHOlCvVexs40LqJRLjemFE0kiWHTRH8cTrQ8dMzdAy mqNPeBA4uc72U933Iy+IQVAlPIfHvd9sSymq1goolS0MtHMSXXVhoPb9iDjAhHdZzMAMJrn+etVu5 SCz9b6J8d9O+J3qr+fcV0fK95pe+ofdhgtEEbr11jDVznmxlnaxIB18zZvqIejCh6Yx72qsVEjNnb mBa4RJ+cTfQWw9I7ViWw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mYlVQ-00259t-SV; Fri, 08 Oct 2021 08:45:28 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mYlVM-00258q-CO for linux-arm-kernel@lists.infradead.org; Fri, 08 Oct 2021 08:45:25 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id C3BE661056; Fri, 8 Oct 2021 08:45:21 +0000 (UTC) Date: Fri, 8 Oct 2021 09:45:18 +0100 From: Catalin Marinas To: Zhaoyang Huang Cc: Will Deacon , Mark Rutland , Suzuki K Poulose , Ionela Voinescu , Quentin Perret , Vladimir Murzin , linux-arm-kernel@lists.infradead.org, Zhaoyang Huang , LKML , Ke Wang , ping.zhou1@unisoc.com Subject: Re: [RFC PATCH] arch: ARM64: add isb before enable pan Message-ID: References: <1633673269-15048-1-git-send-email-huangzhaoyang@gmail.com> <20211008080113.GA441@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211008_014524_465607_ECDCB9C3 X-CRM114-Status: GOOD ( 18.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Oct 08, 2021 at 04:34:12PM +0800, Zhaoyang Huang wrote: > On Fri, Oct 8, 2021 at 4:01 PM Will Deacon wrote: > > On Fri, Oct 08, 2021 at 02:07:49PM +0800, Huangzhaoyang wrote: > > > From: Zhaoyang Huang > > > > > > set_pstate_pan failure is observed in an ARM64 system occasionaly on a reboot > > > test, which can be work around by a msleep on the sw context. We assume > > > suspicious on disorder of previous instr of disabling SW_PAN and add an isb here. > > > > > > PS: > > > The bootup test failed with a invalid TTBR1_EL1 that equals 0x34000000, which is > > > alike racing between on chip PAN and SW_PAN. > > > > Sorry, but I'm struggling to understand the problem here. Please could you > > explain it in more detail? > > > > - Why does a TTBR1_EL1 value of `0x34000000` indicate a race? > > - Can you explain the race that you think might be occurring? > > - Why does an ISB prevent the race? > Please find panic logs[1], related codes[2], sample of debug patch[3] > below. TTBR1_EL1 equals 0x34000000 when panic and can NOT be captured > by the debug patch during retest (all entrances that msr ttbr1_el1 are > under watch) which should work. Adding ISB here to prevent race on > TTBR1 from previous access of sysregs which can affect the msr > result(the test is still ongoing). Could the race be > ARM64_HAS_PAN(automated by core) and SW_PAN. Can you please change the ARM64_HAS_PAN type to ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE? I wonder whether system_uses_ttbr0_pan() changes its output when all CPUs had been brought up and system_uses_hw_pan() returns true. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel