From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C41C2C433F5 for ; Mon, 8 Nov 2021 10:27:29 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8A24761056 for ; Mon, 8 Nov 2021 10:27:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 8A24761056 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=he6f9WYi8V6utADL4X+YlgxBxdqeweLmTtBgdkanZXU=; b=fOyD+6ek+9bWJE JPlqqQ8+E+XZ8A/li9rN0WNW4Kw3Op7Y2MvppI8MRFgmmhBL+PXchtXH1FWnEH/W1NoZu9lZZFQfl NuQ6cRATdrhaZVqeMnt+if+HWW86ytk/4mSd/+vQDq5obNvjjdVISxnDx2khnSkKxo4ozLq+eYSt2 /9ZhoqKovvR87cZjbRII5IvUPJ8Y4hbsHhCdDTvPCRcw1DHSUTuz7Hfp5hn9vaNAahIRpmw919kyi 1ms7F90djL6VIG7imnnXgFmx2eC7X6RjTAcg93K9G2CBQY99MzOb1BMikzg//XJdnxjrWOxqIHHWr qqY0kx0BDEOISiKnDquQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mk1qq-00G2TZ-Qv; Mon, 08 Nov 2021 10:26:08 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mk1qn-00G2SF-DG for linux-arm-kernel@lists.infradead.org; Mon, 08 Nov 2021 10:26:06 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 257AB1FB; Mon, 8 Nov 2021 02:26:01 -0800 (PST) Received: from FVFF77S0Q05N (unknown [10.57.58.140]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C89913F800; Mon, 8 Nov 2021 02:25:58 -0800 (PST) Date: Mon, 8 Nov 2021 10:25:52 +0000 From: Mark Rutland To: Brad Larson Cc: Linux ARM , Arnd Bergmann , Linus Walleij , Bartosz Golaszewski , Mark Brown , Serge Semin , Adrian Hunter , Ulf Hansson , Olof Johansson , "open list:GPIO SUBSYSTEM" , linux-spi , linux-mmc , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux Kernel Mailing List Subject: Re: [PATCH v3 11/11] arm64: dts: Add Pensando Elba SoC support Message-ID: References: <20211025015156.33133-1-brad@pensando.io> <20211025015156.33133-12-brad@pensando.io> <20211025091731.GA2001@C02TD0UTHF1T.local> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211108_022605_604549_B1D8E08C X-CRM114-Status: GOOD ( 18.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Nov 04, 2021 at 03:53:13PM -0700, Brad Larson wrote: > On Mon, Oct 25, 2021 at 2:17 AM Mark Rutland wrote: > > On Sun, Oct 24, 2021 at 06:51:56PM -0700, Brad Larson wrote: > > > + timer { > > > + compatible = "arm,armv8-timer"; > > > + interrupts = > > + IRQ_TYPE_LEVEL_LOW)>, > > > + > > + IRQ_TYPE_LEVEL_LOW)>, > > > + > > + IRQ_TYPE_LEVEL_LOW)>, > > > + > > + IRQ_TYPE_LEVEL_LOW)>; > > > + }; > > > > The GIC_CPU_MASK_SIMPLE() stuff is meant for GICv2, but as below you > > have GICv3, where this is not valid, so this should go. > > > > Also, beware that GIC_CPU_MASK_SIMPLE(1) means a single CPU, which > > doesn't mak sense for the 16 CPUs you have. > > > > Thanks for pointing this out. Elba SoC is a GICv3 implementation and looking > at other device tree files we should be using this: > > timer { > compatible = "arm,armv8-timer"; > interrupts = IRQ_TYPE_LEVEL_LOW)>, > IRQ_TYPE_LEVEL_LOW)>, > IRQ_TYPE_LEVEL_LOW)>, > IRQ_TYPE_LEVEL_LOW)>; > }; No; as above, you should *not* use GIC_CPU_MASK_SIMPLE() at all for GICv3. i.e. > timer { > compatible = "arm,armv8-timer"; > interrupts = , > , > , > ; > }; Please see the GICv3 binding documentation: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml ... and note that it does not have the cpumask field as use by the binding for prior generations of GIC: Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml If you've seen other dts files using GIC_CPU_MASK_SIMPLE() with GICv3, those are incorrect, and need to be fixed. Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel