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[82.27.106.168]) by smtp.gmail.com with ESMTPSA id bo20sm9763810edb.31.2021.11.16.07.42.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Nov 2021 07:42:26 -0800 (PST) Date: Tue, 16 Nov 2021 15:42:05 +0000 From: Jean-Philippe Brucker To: Robin Murphy Cc: robh+dt@kernel.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, will@kernel.org, joro@8bytes.org, mark.rutland@arm.com, jkchen@linux.alibaba.com, leo.yan@linaro.org, uchida.jun@socionext.com Subject: Re: [PATCH 0/2] perf/smmuv3: Support devicetree Message-ID: References: <20211116113536.69758-1-jean-philippe@linaro.org> <3b5cb536-5a11-5096-4369-cec3d369ec52@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <3b5cb536-5a11-5096-4369-cec3d369ec52@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211116_074228_391713_9276E673 X-CRM114-Status: GOOD ( 21.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Nov 16, 2021 at 12:02:47PM +0000, Robin Murphy wrote: > On 2021-11-16 11:35, Jean-Philippe Brucker wrote: > > Add devicetree binding for the SMMUv3 PMU, called Performance Monitoring > > Counter Group (PMCG) in the spec. Each SMMUv3 implementation can have > > multiple independent PMCGs, for example one for the Translation Control > > Unit (TCU) and one per Translation Buffer Unit (TBU). > > > > I previously sent the binding as reply to Jay Chen's thread implementing > > device tree support [1]. This posting addresses the comments from that > > thread. > > Ha, I'd also resurrected this and was planning to post it at some point this > week[0] - you should have said :) Ah sorry about that, I just resent because there was some demand for it at Linaro > > Patch 1 adds two compatible strings. "arm,smmu-v3-pmcg" is common to all > > PMCGs. "hisilicon,smmu-v3-pmcg-hip08" allows to support the same quirk > > as IORT for that implementation (see patch 2). We'll probably want to > > also introduce compatible strings for each implementation that has > > additional perf events. For example the MMU-600 implementation has > > different events for TCU and TBU PMCGs [2], but both components have the > > same device IDs. So the driver could differentiate them if they had two > > distinct compatible strings such as "arm,mmu-600-pmcg-tbu" and > > "arm,mmu-600-pmcg-tcu". > > Actually it only needs a general MMU-600 compatible, since once you know > it's an Arm Ltd. implementation, you can assume the pattern for the IMP_DEF > ID registers to figure out the rest. It might be an error in the MMU-600 spec specifically, both TBU and TCU PMU registers have a 0x83 PIDR0, where I think the TBU should be 0x84 (the revC model uses that value). It's possible that the implementation actually has 0x84 instead. Thanks, Jean _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel