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[66.90.148.213]) by smtp.gmail.com with ESMTPSA id t5sm2422654ool.10.2021.11.29.13.06.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Nov 2021 13:06:12 -0800 (PST) Received: (nullmailer pid 609039 invoked by uid 1000); Mon, 29 Nov 2021 21:06:12 -0000 Date: Mon, 29 Nov 2021 15:06:12 -0600 From: Rob Herring To: Thierry Reding Cc: Robin Murphy , Jon Hunter , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org Subject: Re: [PATCH 2/2] arm64: tegra: Describe Tegra234 CPU hierarchy Message-ID: References: <20211112131904.3683428-1-thierry.reding@gmail.com> <20211112131904.3683428-2-thierry.reding@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211112131904.3683428-2-thierry.reding@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211129_130615_052071_2B2C2B12 X-CRM114-Status: GOOD ( 16.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Nov 12, 2021 at 02:19:04PM +0100, Thierry Reding wrote: > From: Thierry Reding > > The NVIDIA Tegra234 SoC has 3 clusters of 4 Cortex-A78AE CPU cores each, > for a total of 12 CPUs. Each CPU has 64 KiB instruction and data caches > with each cluster having an additional 256 KiB unified L2 cache and a 2 > MiB L3 cache. > > Signed-off-by: Thierry Reding > --- > arch/arm64/boot/dts/nvidia/tegra234.dtsi | 365 ++++++++++++++++++++++- > 1 file changed, 363 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi > index 104e5fdd5f8a..db24f48edc9f 100644 > --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi > +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi > @@ -736,12 +736,373 @@ cpus { > #address-cells = <1>; > #size-cells = <0>; > > - cpu@0 { > + cpu0_0: cpu@0 { > + compatible = "arm,cortex-a78"; > device_type = "cpu"; > - reg = <0x000>; > + reg = <0x00000>; > > enable-method = "psci"; > + > + i-cache-size = <65536>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <65536>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; Isn't all this discoverable? > + next-level-cache = <&l2c0_0>; > + }; > + > + cpu0_1: cpu@100 { > + compatible = "arm,cortex-a78"; > + device_type = "cpu"; > + reg = <0x00100>; > + > + enable-method = "psci"; > + > + i-cache-size = <65536>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <65536>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&l2c0_1>; > + }; > + > + cpu0_2: cpu@200 { > + compatible = "arm,cortex-a78"; > + device_type = "cpu"; > + reg = <0x00200>; > + > + enable-method = "psci"; > + > + i-cache-size = <65536>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <65536>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&l2c0_2>; > + }; > + > + cpu0_3: cpu@300 { > + compatible = "arm,cortex-a78"; > + device_type = "cpu"; > + reg = <0x00300>; > + > + enable-method = "psci"; > + > + i-cache-size = <65536>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <65536>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&l2c0_3>; > + }; > + > + cpu1_0: cpu@10000 { > + compatible = "arm,cortex-a78"; > + device_type = "cpu"; > + reg = <0x10000>; > + > + enable-method = "psci"; > + > + i-cache-size = <65536>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <65536>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&l2c1_0>; > + }; > + > + cpu1_1: cpu@10100 { > + compatible = "arm,cortex-a78"; > + device_type = "cpu"; > + reg = <0x10100>; > + > + enable-method = "psci"; > + > + i-cache-size = <65536>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <65536>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&l2c1_1>; > + }; > + > + cpu1_2: cpu@10200 { > + compatible = "arm,cortex-a78"; > + device_type = "cpu"; > + reg = <0x10200>; > + > + enable-method = "psci"; > + > + i-cache-size = <65536>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <65536>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&l2c1_2>; > + }; > + > + cpu1_3: cpu@10300 { > + compatible = "arm,cortex-a78"; > + device_type = "cpu"; > + reg = <0x10300>; > + > + enable-method = "psci"; > + > + i-cache-size = <65536>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <65536>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&l2c1_3>; > + }; > + > + cpu2_0: cpu@20000 { > + compatible = "arm,cortex-a78"; > + device_type = "cpu"; > + reg = <0x20000>; > + > + enable-method = "psci"; > + > + i-cache-size = <65536>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <65536>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&l2c2_0>; > + }; > + > + cpu2_1: cpu@20100 { > + compatible = "arm,cortex-a78"; > + device_type = "cpu"; > + reg = <0x20100>; > + > + enable-method = "psci"; > + > + i-cache-size = <65536>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <65536>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&l2c2_1>; > + }; > + > + cpu2_2: cpu@20200 { > + compatible = "arm,cortex-a78"; > + device_type = "cpu"; > + reg = <0x20200>; > + > + enable-method = "psci"; > + > + i-cache-size = <65536>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <65536>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&l2c2_2>; > + }; > + > + cpu2_3: cpu@20300 { > + compatible = "arm,cortex-a78"; > + device_type = "cpu"; > + reg = <0x20300>; > + > + enable-method = "psci"; > + > + i-cache-size = <65536>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <65536>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&l2c2_3>; > + }; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0_0>; > + }; > + > + core1 { > + cpu = <&cpu0_1>; > + }; > + > + core2 { > + cpu = <&cpu0_2>; > + }; > + > + core3 { > + cpu = <&cpu0_3>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&cpu1_0>; > + }; > + > + core1 { > + cpu = <&cpu1_1>; > + }; > + > + core2 { > + cpu = <&cpu1_2>; > + }; > + > + core3 { > + cpu = <&cpu1_3>; > + }; > + }; > + > + cluster2 { > + core0 { > + cpu = <&cpu2_0>; > + }; > + > + core1 { > + cpu = <&cpu2_1>; > + }; > + > + core2 { > + cpu = <&cpu2_2>; > + }; > + > + core3 { > + cpu = <&cpu2_3>; > + }; > + }; > + }; > + > + l2c0_0: l2-cache00 { > + cache-size = <262144>; > + cache-line-size = <64>; > + cache-sets = <512>; > + cache-unified; > + next-level-cache = <&l3c0>; > + }; > + > + l2c0_1: l2-cache01 { > + cache-size = <262144>; > + cache-line-size = <64>; > + cache-sets = <512>; > + cache-unified; > + next-level-cache = <&l3c0>; > }; > + > + l2c0_2: l2-cache02 { > + cache-size = <262144>; > + cache-line-size = <64>; > + cache-sets = <512>; > + cache-unified; > + next-level-cache = <&l3c0>; > + }; > + > + l2c0_3: l2-cache03 { > + cache-size = <262144>; > + cache-line-size = <64>; > + cache-sets = <512>; > + cache-unified; > + next-level-cache = <&l3c0>; > + }; > + > + l2c1_0: l2-cache10 { > + cache-size = <262144>; > + cache-line-size = <64>; > + cache-sets = <512>; > + cache-unified; > + next-level-cache = <&l3c1>; > + }; > + > + l2c1_1: l2-cache11 { > + cache-size = <262144>; > + cache-line-size = <64>; > + cache-sets = <512>; > + cache-unified; > + next-level-cache = <&l3c1>; > + }; > + > + l2c1_2: l2-cache12 { > + cache-size = <262144>; > + cache-line-size = <64>; > + cache-sets = <512>; > + cache-unified; > + next-level-cache = <&l3c1>; > + }; > + > + l2c1_3: l2-cache13 { > + cache-size = <262144>; > + cache-line-size = <64>; > + cache-sets = <512>; > + cache-unified; > + next-level-cache = <&l3c1>; > + }; > + > + l2c2_0: l2-cache20 { > + cache-size = <262144>; > + cache-line-size = <64>; > + cache-sets = <512>; > + cache-unified; > + next-level-cache = <&l3c2>; > + }; > + > + l2c2_1: l2-cache21 { > + cache-size = <262144>; > + cache-line-size = <64>; > + cache-sets = <512>; > + cache-unified; > + next-level-cache = <&l3c2>; > + }; > + > + l2c2_2: l2-cache22 { > + cache-size = <262144>; > + cache-line-size = <64>; > + cache-sets = <512>; > + cache-unified; > + next-level-cache = <&l3c2>; > + }; > + > + l2c2_3: l2-cache23 { > + cache-size = <262144>; > + cache-line-size = <64>; > + cache-sets = <512>; > + cache-unified; > + next-level-cache = <&l3c2>; > + }; > + > + l3c0: l3-cache0 { > + cache-size = <2097152>; > + cache-line-size = <64>; > + cache-sets = <2048>; > + }; > + > + l3c1: l3-cache1 { > + cache-size = <2097152>; > + cache-line-size = <64>; > + cache-sets = <2048>; > + }; > + > + l3c2: l3-cache2 { > + cache-size = <2097152>; > + cache-line-size = <64>; > + cache-sets = <2048>; > + }; > + }; > + > + pmu { > + compatible = "arm,armv8-pmuv3"; > + interrupts = ; > + status = "okay"; That's the default. > }; > > psci { > -- > 2.33.1 > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel