From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Cc: Jiri Slaby <jirislaby@kernel.org>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-arm-msm@vger.kernel.org, quic_eberman@quicinc.com,
quic_tsoni@quicinc.com,
Shanker Donthineni <shankerd@codeaurora.org>,
Adam Wallis <awallis@codeaurora.org>,
Timur Tabi <timur@codeaurora.org>,
Elliot Berman <eberman@codeaurora.org>
Subject: Re: [RESEND PATCHv2] tty: hvc: dcc: Bind driver to core0 for reads and writes
Date: Wed, 8 Dec 2021 08:00:09 +0100 [thread overview]
Message-ID: <YbBX+cLRhJ5T+hBq@kroah.com> (raw)
In-Reply-To: <20211208063847.27174-1-quic_saipraka@quicinc.com>
On Wed, Dec 08, 2021 at 12:08:47PM +0530, Sai Prakash Ranjan wrote:
> From: Shanker Donthineni <shankerd@codeaurora.org>
>
> Some debuggers, such as Trace32 from Lauterbach GmbH, do not handle
> reads/writes from/to DCC on secondary cores. Each core has its
> own DCC device registers, so when a core reads or writes from/to DCC,
> it only accesses its own DCC device. Since kernel code can run on
> any core, every time the kernel wants to write to the console, it
> might write to a different DCC.
>
> In SMP mode, Trace32 creates multiple windows, and each window shows
> the DCC output only from that core's DCC. The result is that console
> output is either lost or scattered across windows.
>
> Selecting this option will enable code that serializes all console
> input and output to core 0. The DCC driver will create input and
> output FIFOs that all cores will use. Reads and writes from/to DCC
> are handled by a workqueue that runs only core 0.
>
> Link: https://lore.kernel.org/lkml/1435344756-20901-1-git-send-email-timur@codeaurora.org/
> Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
> Acked-by: Adam Wallis <awallis@codeaurora.org>
> Signed-off-by: Timur Tabi <timur@codeaurora.org>
> Signed-off-by: Elliot Berman <eberman@codeaurora.org>
> Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
> ---
>
> Resending this v2 since earlier one had a typo in the variable type.
>
> Changes in v2:
> * Checkpatch warning fixes.
> * Use of IS_ENABLED macros instead of ifdefs.
>
> I also thought of making it depends on !HOTPLUG_CPU since it is broken
> in case core0 is hotplugged off, but apparently HOTPLUG_CPU kconfig
> has weird dependency issues, i.e., gets selected by CONFIG_PM and others.
> So it will be almost like this feature won't be selectable at all if
> I add !HOTPLUG_CPU kconfig dependency. Also HVC_DCC is a debug feature
> where we need Trace32 like tools to access DCC windows in which case
> these shortcomings can be expected since manual intervention is required
> anyways for attaching a core to Trace32, so it won't matter much.
But your code will break on systems when cpu 0 goes away, so this isn't
going to work well at all. Please make this work for any cpu or handle
the case when the cpu it is running on goes away.
Also, this REALLY looks like you are trying to fix the kernel for a
crazy userspace program. Why not fix the userspace program instead?
Isn't that easier and then that way it will work for any kernel version?
thanks,
greg k-h
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next prev parent reply other threads:[~2021-12-08 7:02 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-08 6:38 [RESEND PATCHv2] tty: hvc: dcc: Bind driver to core0 for reads and writes Sai Prakash Ranjan
2021-12-08 7:00 ` Greg Kroah-Hartman [this message]
2021-12-08 7:21 ` Sai Prakash Ranjan
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