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[66.90.148.213]) by smtp.gmail.com with ESMTPSA id y192sm745006oie.21.2021.12.08.10.16.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Dec 2021 10:16:02 -0800 (PST) Received: (nullmailer pid 85688 invoked by uid 1000); Wed, 08 Dec 2021 18:16:01 -0000 Date: Wed, 8 Dec 2021 12:16:01 -0600 From: Rob Herring To: Robin Murphy Cc: will@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, suzuki.poulose@arm.com, thierry.reding@gmail.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: Re: [PATCH 4/5] dt-bindings: perf: Convert Arm DSU to schema Message-ID: References: <9530f441a62c72c5a22a7b555ea42bbcd3b145a1.1638900542.git.robin.murphy@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <9530f441a62c72c5a22a7b555ea42bbcd3b145a1.1638900542.git.robin.murphy@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211208_101604_642892_A5886F50 X-CRM114-Status: GOOD ( 20.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Dec 07, 2021 at 06:20:42PM +0000, Robin Murphy wrote: > Convert the DSU binding to schema, as one does. > > Signed-off-by: Robin Murphy > --- > .../devicetree/bindings/arm/arm-dsu-pmu.txt | 27 ------------ > .../devicetree/bindings/perf/arm,dsu-pmu.yaml | 41 +++++++++++++++++++ > 2 files changed, 41 insertions(+), 27 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt > create mode 100644 Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml > > diff --git a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt > deleted file mode 100644 > index 6efabba530f1..000000000000 > --- a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt > +++ /dev/null > @@ -1,27 +0,0 @@ > -* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) > - > -ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores > -with a shared L3 memory system, control logic and external interfaces to > -form a multicore cluster. The PMU enables to gather various statistics on > -the operations of the DSU. The PMU provides independent 32bit counters that > -can count any of the supported events, along with a 64bit cycle counter. > -The PMU is accessed via CPU system registers and has no MMIO component. > - > -** DSU PMU required properties: > - > -- compatible : should be one of : > - > - "arm,dsu-pmu" > - > -- interrupts : Exactly 1 SPI must be listed. > - > -- cpus : List of phandles for the CPUs connected to this DSU instance. > - > - > -** Example: > - > -dsu-pmu-0 { > - compatible = "arm,dsu-pmu"; > - interrupts = ; > - cpus = <&cpu_0>, <&cpu_1>; > -}; > diff --git a/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml > new file mode 100644 > index 000000000000..b78b6b0fce66 > --- /dev/null > +++ b/Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml > @@ -0,0 +1,41 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright 2021 Arm Ltd. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) > + > +maintainers: > + - Suzuki K Poulose > + - Robin Murphy > + > +description: > + ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores with a shared > + L3 memory system, control logic and external interfaces to form a multicore > + cluster. The PMU enables gathering various statistics on the operation of the > + DSU. The PMU provides independent 32-bit counters that can count any of the > + supported events, along with a 64-bit cycle counter. The PMU is accessed via > + CPU system registers and has no MMIO component. > + > +properties: > + compatible: > + const: "arm,dsu-pmu" Don't need quotes. > + > + interrupts: > + items: > + description: nCLUSTERPMUIRQ interrupt - description: nCLUSTERPMUIRQ interrupt > + > + cpus: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + minitems: 1 > + maxitems: 8 > + description: List of phandles for the CPUs connected to this DSU instance. > + > +required: > + - compatible > + - interrupts > + - cpus > + > +additionalProperties: false > -- > 2.28.0.dirty > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel