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Tue, 14 Dec 2021 04:27:19 -0800 (PST) Date: Tue, 14 Dec 2021 13:27:16 +0100 From: Thierry Reding To: Robin Murphy Cc: Rob Herring , Jon Hunter , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org, Mark Rutland , Will Deacon Subject: Re: [PATCH 2/2] arm64: tegra: Describe Tegra234 CPU hierarchy Message-ID: References: <20211112131904.3683428-1-thierry.reding@gmail.com> <20211112131904.3683428-2-thierry.reding@gmail.com> <8ea071d7-a8ff-813a-6268-7445dbbf0c1a@arm.com> MIME-Version: 1.0 In-Reply-To: <8ea071d7-a8ff-813a-6268-7445dbbf0c1a@arm.com> User-Agent: Mutt/2.1.3 (987dde4c) (2021-09-10) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211214_042723_819127_9EB57250 X-CRM114-Status: GOOD ( 21.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============0604510486877938630==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============0604510486877938630== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="AypUwBlYQnwhP8aV" Content-Disposition: inline --AypUwBlYQnwhP8aV Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Nov 29, 2021 at 10:53:37PM +0000, Robin Murphy wrote: > On 2021-11-29 21:06, Rob Herring wrote: > > On Fri, Nov 12, 2021 at 02:19:04PM +0100, Thierry Reding wrote: > > > From: Thierry Reding > > >=20 > > > The NVIDIA Tegra234 SoC has 3 clusters of 4 Cortex-A78AE CPU cores ea= ch, > > > for a total of 12 CPUs. Each CPU has 64 KiB instruction and data cach= es > > > with each cluster having an additional 256 KiB unified L2 cache and a= 2 > > > MiB L3 cache. > > >=20 > > > Signed-off-by: Thierry Reding > > > --- > > > arch/arm64/boot/dts/nvidia/tegra234.dtsi | 365 ++++++++++++++++++++= ++- > > > 1 file changed, 363 insertions(+), 2 deletions(-) > > >=20 > > > diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/bo= ot/dts/nvidia/tegra234.dtsi > > > index 104e5fdd5f8a..db24f48edc9f 100644 > > > --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi > > > +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi > > > @@ -736,12 +736,373 @@ cpus { > > > #address-cells =3D <1>; > > > #size-cells =3D <0>; > > > - cpu@0 { > > > + cpu0_0: cpu@0 { > > > + compatible =3D "arm,cortex-a78"; > > > device_type =3D "cpu"; > > > - reg =3D <0x000>; > > > + reg =3D <0x00000>; > > > enable-method =3D "psci"; > > > + > >=20 > > > + i-cache-size =3D <65536>; > > > + i-cache-line-size =3D <64>; > > > + i-cache-sets =3D <256>; > > > + d-cache-size =3D <65536>; > > > + d-cache-line-size =3D <64>; > > > + d-cache-sets =3D <256>; > >=20 > > Isn't all this discoverable? >=20 > No. The required parameters for cache maintenance by set/way are > discoverable from the CTR, and if you're particularly lucky they might ev= en > happen to reflect the underlying physical cache structures, but there's > absolutely no guarantee of that, and there definitely exist cases where t= hey > don't. >=20 > [...] > > > + pmu { > > > + compatible =3D "arm,armv8-pmuv3"; >=20 > Oh, I'd missed this - per the current state of things, we should really h= ave > a proper compatible for the PMU as well. Good catch! I've changed this to arm,cortex-a78-pmu since that's what Tegra234 has. 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