From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1CF1AC433F5 for ; Wed, 12 Jan 2022 10:34:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ftDM6Og4icgp38MP+kgrkEAJY7+6BedMNMMP+ZSS+q0=; b=cMck/eanKX2XyH 5O6IiVAyM2e45RpnHcYR8Yegd3PuPhNEkTqLdECVZ6gNrX/CJS/IOdKN9ADk+07J/Ho5oJFKn45Nf LGBKgwZymzEAJtEVuMahXdEDpcM9Qp4xwhvze5sUP5ATGKVq40c83XssSDKXO603f9/3SxGsTgESO eUJMlWjc8BsVf9npD6EeTFWhZmixVPAI3n3SkG6pOjgax1q0q2LEFXSFg/7f4u5BDN2eAYfzlX5ae 1sQkI+Li6ejBaAeIj4bZZaojY5qPZZ3HVkK0KFAgqKEX9sBBzXFHF9gduUm/NEGtU1YBMrWpYrE1i vvwNqUoRbtlgUelEVZjw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n7aw5-0028A0-Df; Wed, 12 Jan 2022 10:32:57 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n7aw0-002889-Jy for linux-arm-kernel@lists.infradead.org; Wed, 12 Jan 2022 10:32:54 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 11A131FB; Wed, 12 Jan 2022 02:32:51 -0800 (PST) Received: from FVFF77S0Q05N (unknown [10.57.1.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 89C3F3F5A1; Wed, 12 Jan 2022 02:32:49 -0800 (PST) Date: Wed, 12 Jan 2022 10:32:44 +0000 From: Mark Rutland To: Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Mathieu Poirier , Suzuki Poulose , coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] arm64: errata: Update ARM64_ERRATUM_[2119858|2224489] with Cortex-X2 ranges Message-ID: References: <1641980099-20315-1-git-send-email-anshuman.khandual@arm.com> <1641980099-20315-3-git-send-email-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1641980099-20315-3-git-send-email-anshuman.khandual@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220112_023252_788733_6A4BAA68 X-CRM114-Status: GOOD ( 23.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Anshuman, On Wed, Jan 12, 2022 at 03:04:59PM +0530, Anshuman Khandual wrote: > Errata ARM64_ERRATUM_[2119858|2224489] also affect some Cortex-X2 ranges as > well. Lets update these errata definition and detection to accommodate all > new Cortex-X2 based cpu MIDR ranges. > > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Mathieu Poirier > Cc: Suzuki Poulose > Cc: coresight@lists.linaro.org > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Signed-off-by: Anshuman Khandual > --- > arch/arm64/Kconfig | 12 ++++++------ > arch/arm64/kernel/cpu_errata.c | 2 ++ > 2 files changed, 8 insertions(+), 6 deletions(-) I think you've misssed Documentation/arm64/silicon-errata.rst -- for other common errata we add lines for each affected part, e.g. as we do for ARM64_ERRATUM_1418040. Other than that, this looks good to me! Thanks, Mark. > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index c4207cf9bb17..d8046c832225 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -671,14 +671,14 @@ config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE > bool > > config ARM64_ERRATUM_2119858 > - bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode" > + bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" > default y > depends on CORESIGHT_TRBE > select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE > help > - This option adds the workaround for ARM Cortex-A710 erratum 2119858. > + This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. > > - Affected Cortex-A710 cores could overwrite up to 3 cache lines of trace > + Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace > data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in > the event of a WRAP event. > > @@ -761,14 +761,14 @@ config ARM64_ERRATUM_2253138 > If unsure, say Y. > > config ARM64_ERRATUM_2224489 > - bool "Cortex-A710: 2224489: workaround TRBE writing to address out-of-range" > + bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" > depends on CORESIGHT_TRBE > default y > select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE > help > - This option adds the workaround for ARM Cortex-A710 erratum 2224489. > + This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. > > - Affected Cortex-A710 cores might write to an out-of-range address, not reserved > + Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved > for TRBE. Under some conditions, the TRBE might generate a write to the next > virtually addressed page following the last page of the TRBE address space > (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index 9e1c1aef9ebd..29cc062a4153 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -347,6 +347,7 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { > #endif > #ifdef CONFIG_ARM64_ERRATUM_2119858 > MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), > + MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0), > #endif > {}, > }; > @@ -371,6 +372,7 @@ static struct midr_range trbe_write_out_of_range_cpus[] = { > #endif > #ifdef CONFIG_ARM64_ERRATUM_2224489 > MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), > + MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0), > #endif > {}, > }; > -- > 2.20.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel