[bootwrapper PATCH v2 04/13] aarch32: add coprocessor accessors

Mark Rutland
2022-01-14T10:59:14Z

We open code the use of mrc/mcr for specific registers, which is
somewhat tedious. Add macros to do this generically, along with a helper
to extract a specific register field. Existing C usage is converted to
the new helpers, and register definitions moved to a common location.

There should be no functional change as a result of this patch.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
arch/aarch32/include/asm/cpu.h | 45 ++++++++++++++++++++-----------
arch/aarch32/include/asm/gic-v3.h | 6 +++--
2 files changed, 34 insertions(+), 17 deletions(-)

diff --git a/arch/aarch32/include/asm/cpu.h b/arch/aarch32/include/asm/cpu.h
index 105cae5..d691c7b 100644
--- a/arch/aarch32/include/asm/cpu.h
+++ b/arch/aarch32/include/asm/cpu.h
@@ -9,9 +9,13 @@
#ifndef __ASM_AARCH32_CPU_H
#define __ASM_AARCH32_CPU_H

+#include <bits.h>
+
#define MPIDR_ID_BITS 0x00ffffff
#define MPIDR_INVALID (-1)

+#define ID_PFR1_GIC BITS(31, 28)
+
/* Only RES1 bits and CP15 barriers for the kernel */
#define HSCTLR_KERNEL (3 << 28 | 3 << 22 | 1 << 18 | 1 << 16 | 1 << 11 | 3 << 4)
#define SCTLR_KERNEL (3 << 22 | 1 << 11 | 1 << 5 | 3 << 4)
@@ -40,32 +44,43 @@
#define sevl() asm volatile ("sev" : : : "memory")
#endif

-static inline unsigned long read_mpidr(void)
-{
- unsigned long mpidr;
+#define MPIDR "p15, 0, %0, c0, c0, 5"
+#define ID_PFR1 "p15, 0, %0, c0, c1, 1"
+#define ICIALLU "p15, 0, %0, c7, c5, 0"

- asm volatile ("mrc p15, 0, %0, c0, c0, 5\n" : "=r" (mpidr));
- return mpidr & MPIDR_ID_BITS;
-}
+#define ICC_SRE "p15, 6, %0, c12, c12, 5"
+#define ICC_CTLR "p15, 6, %0, c12, c12, 4"

-static inline uint32_t read_id_pfr1(void)
-{
- uint32_t val;
+#define mrc(reg) \
+({ \
+ unsigned long __mrc_val; \
+ asm volatile("mrc " reg : "=r" (__mrc_val)); \
+ __mrc_val; \
+})

- asm volatile ("mrc p15, 0, %0, c0, c1, 1\n" : "=r" (val));
- return val;
+#define mcr(reg, val) \
+do { \
+ unsigned long __mcr_val = val; \
+ asm volatile("mcr " reg : : "r" (__mcr_val)); \
+} while (0)
+
+
+#define mrc_field(reg, field) \
+ BITS_EXTRACT(mrc(reg), (reg##_##field))
+
+static inline unsigned long read_mpidr(void)
+{
+ return mrc(MPIDR) & MPIDR_ID_BITS;
}

static inline void iciallu(void)
{
- uint32_t val = 0;
-
- asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (val));
+ mcr(ICIALLU, 0);
}

static inline int has_gicv3_sysreg(void)
{
- return !!((read_id_pfr1() >> 28) & 0xf);
+ return !!mrc_field(ID_PFR1, GIC);
}

#endif /* __ASSEMBLY__ */
diff --git a/arch/aarch32/include/asm/gic-v3.h b/arch/aarch32/include/asm/gic-v3.h
index 65f38de..b28136a 100644
--- a/arch/aarch32/include/asm/gic-v3.h
+++ b/arch/aarch32/include/asm/gic-v3.h
@@ -9,14 +9,16 @@
#ifndef __ASM_AARCH32_GICV3_H
#define __ASM_AARCH32_GICV3_H

+#include <asm/cpu.h>
+
static inline void gic_write_icc_sre(uint32_t val)
{
- asm volatile ("mcr p15, 6, %0, c12, c12, 5" : : "r" (val));
+ mcr(ICC_SRE, val);
}

static inline void gic_write_icc_ctlr(uint32_t val)
{
- asm volatile ("mcr p15, 6, %0, c12, c12, 4" : : "r" (val));
+ mcr(ICC_CTLR, val);
}

#endif
--
2.30.2