From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 60C8EC433EF for ; Tue, 1 Feb 2022 12:21:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=o5VV3tWtfTmp0IV/EPCGmEuZDbQun4t9zmSGXZatnSg=; b=xSXcdExqf+le5G wSzx6xy6SWAJ31O3zyiBdyM6PLx1nEEsZeYt5QOgsEHXyzxStArgzk7iTVRhflvu5ZvNLIUkfWyk6 IZKsnmVjFvJrIT8fu5fWy26A+0dw+IZ6OGqS8tnwyVdZlGTJNcJvUKioysVEkgotUH3JIZ1NHDfMM gLhXvxFmKVk/+Nq8Ej2phujgZxNorMe6wlpOTkYpbosXkHHBFR2BDqfHphLOMDYEh/FdIgWZ0L2jD /vNr9I9mKmO4TRwF6BQlSghmS2h/pbvYbm2RVGgEXsq4XXDzIsF1tZjf//9DtvNj3bUyy+Tkio0Hp m58iNXkYvK76l8DUIEwg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nEs8U-00C2bj-DT; Tue, 01 Feb 2022 12:19:50 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nEs8Q-00C2ar-Ah for linux-arm-kernel@lists.infradead.org; Tue, 01 Feb 2022 12:19:47 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3541A113E; Tue, 1 Feb 2022 04:19:45 -0800 (PST) Received: from FVFF77S0Q05N (unknown [10.57.8.51]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 93B393F73B; Tue, 1 Feb 2022 04:19:44 -0800 (PST) Date: Tue, 1 Feb 2022 12:19:42 +0000 From: Mark Rutland To: Vladimir Murzin Cc: linux-arm-kernel@lists.infradead.org Subject: Re: [bootwrapper PATCH] aarch64: Recognize PAuth QARMA3 Message-ID: References: <20220128160214.92297-1-vladimir.murzin@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220128160214.92297-1-vladimir.murzin@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220201_041946_437547_88736FB4 X-CRM114-Status: GOOD ( 18.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jan 28, 2022 at 04:02:14PM +0000, Vladimir Murzin wrote: > QARMA3 is relaxed version of the QARMA5 algorithm which expected to > reduce the latency of calculation while still delivering a suitable > level of security. > > Support for QARMA3 can be discovered via ID_AA64ISAR2_EL1 [1] > > APA3, bits [15:12] Indicates whether the QARMA3 algorithm is > implemented in the PE for address authentication in > AArch64 state. > > GPA3, bits [11:8] Indicates whether the QARMA3 algorithm is > implemented in the PE for generic code > authentication in AArch64 state. > > [1] https://developer.arm.com/documentation/ddi0601/2021-12/AArch64-Registers/ID-AA64ISAR2-EL1--AArch64-Instruction-Set-Attribute-Register-2?lang=en > > Signed-off-by: Vladimir Murzin Thanks; applied. Mark. > --- > arch/aarch64/include/asm/cpu.h | 5 +++++ > arch/aarch64/init.c | 14 +++++++++----- > 2 files changed, 14 insertions(+), 5 deletions(-) > > diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h > index 1be2d54..ce80b6e 100644 > --- a/arch/aarch64/include/asm/cpu.h > +++ b/arch/aarch64/include/asm/cpu.h > @@ -63,6 +63,9 @@ > #define ID_AA64ISAR1_EL1_GPA BITS(27, 24) > #define ID_AA64ISAR1_EL1_GPI BITS(31, 28) > > +#define ID_AA64ISAR2_EL1_GPA3 BITS(11, 8) > +#define ID_AA64ISAR2_EL1_APA3 BITS(15, 12) > + > #define ID_AA64MMFR0_EL1_FGT BITS(59, 56) > #define ID_AA64MMFR0_EL1_ECV BITS(63, 60) > > @@ -104,6 +107,8 @@ > #define ZCR_EL3 s3_6_c1_c2_0 > #define ZCR_EL3_LEN_MAX 0xf > > +#define ID_AA64ISAR2_EL1 s3_0_c0_c6_2 > + > #define SCTLR_EL1_CP15BEN (1 << 5) > > #ifdef KERNEL_32 > diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c > index 6677f2b..aa58567 100644 > --- a/arch/aarch64/init.c > +++ b/arch/aarch64/init.c > @@ -30,12 +30,16 @@ static inline bool kernel_is_32bit(void) > > static inline bool cpu_has_pauth(void) > { > - const unsigned long id_pauth = ID_AA64ISAR1_EL1_APA | > - ID_AA64ISAR1_EL1_API | > - ID_AA64ISAR1_EL1_GPA | > - ID_AA64ISAR1_EL1_GPI; > + const unsigned long isar1_pauth = ID_AA64ISAR1_EL1_APA | > + ID_AA64ISAR1_EL1_API | > + ID_AA64ISAR1_EL1_GPA | > + ID_AA64ISAR1_EL1_GPI; > > - return mrs(ID_AA64ISAR1_EL1) & id_pauth; > + const unsigned long isar2_pauth = ID_AA64ISAR2_EL1_APA3 | > + ID_AA64ISAR2_EL1_GPA3; > + > + return (mrs(ID_AA64ISAR1_EL1) & isar1_pauth) || > + (mrs(ID_AA64ISAR2_EL1) & isar2_pauth); > } > > void cpu_init_el3(void) > -- > 2.7.4 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel