From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4ADCAC433FE for ; Tue, 1 Feb 2022 18:18:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=JIU4UGH1CQ6CuwSpnLS7zPhVi6dy/ex+bQa4jE4KczM=; b=fzAT8QnJmKXH3B 7IthtOJL97qnICiWMSjyZzIUnzNgVcdlP9SvFwYtn41cVHs/p04CgRWTz/lh/wwYRRTeGGTv+Mip4 utDOZK1ICUvWdvpYdEbK+xbqdHg7x8bj7tC9o14FAVARBbC8MmdC8b8DYyPqh1NCNaVvFHHTMkeZy tB2XxiwVFS165M+8vP0TydwVMH332HVMruTRfXfsOHyjs1EPnKsFQe2TvyYJwJoLCtwygYAS6TkiW 3+D9RvIOtfhIwskAlzzu5Aho0d5+fhO9oIQqRg+4LwdUYfQOpOm9SHm/kKMFgHFxZeSJR4LbOBJ7B 9gCDhqJ/oUMq8JbwFL6Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nExiE-00DJ9m-DP; Tue, 01 Feb 2022 18:17:06 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nExiB-00DJ97-28 for linux-arm-kernel@lists.infradead.org; Tue, 01 Feb 2022 18:17:04 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 00B8911B3; Tue, 1 Feb 2022 10:17:01 -0800 (PST) Received: from FVFF77S0Q05N (unknown [10.57.8.51]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 632973F40C; Tue, 1 Feb 2022 10:17:00 -0800 (PST) Date: Tue, 1 Feb 2022 18:16:58 +0000 From: Mark Rutland To: broonie@kernel.org Cc: linux-arm-kernel@lists.infradead.org Subject: Re: [boot-wrapper PATCH 2/2] aarch64: Enable use of SME by EL2 and below Message-ID: References: <20220201172132.2399026-1-broonie@kernel.org> <20220201172132.2399026-2-broonie@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220201172132.2399026-2-broonie@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220201_101703_227496_38CED554 X-CRM114-Status: GOOD ( 25.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Mark, On Tue, Feb 01, 2022 at 05:21:32PM +0000, broonie@kernel.org wrote: > From: Mark Brown > > Allow lower ELs to use SME when booted on a system that support it. This > requires us to set two new bits, one in each of SCR_EL3 and CPTR_EL3, set > the maximum vector length in a similar fashion to SVE and if the optional > FA64 feature is present then set another feature bit in the new SMCR > register. This looks good to me. I'll wait a day or so to allow others to review, but if no-one shouts I'll apply this (along with patch 1) before the end of the week. There's one trivial fixup I intend to make when applying (noted below), but regardless this looks good structurally and value-wise, so no need to respin unless someone shouts. I checked the register encodings and bit definitions against developer.arm.com: * CPTR_EL3 https://developer.arm.com/documentation/ddi0601/2021-12/AArch64-Registers/CPTR-EL3--Architectural-Feature-Trap-Register--EL3-?lang=en * ID_AA64PFR1_EL1 https://developer.arm.com/documentation/ddi0601/2021-12/AArch64-Registers/ID-AA64PFR1-EL1--AArch64-Processor-Feature-Register-1?lang=en * ID_AA64SMFR0_EL1 https://developer.arm.com/documentation/ddi0601/2021-12/AArch64-Registers/ID-AA64SMFR0-EL1--SME-Feature-ID-register-0?lang=en * SCR_EL3 https://developer.arm.com/documentation/ddi0601/2021-12/AArch64-Registers/SCR-EL3--Secure-Configuration-Register?lang=en > > Signed-off-by: Mark Brown > --- > arch/aarch64/include/asm/cpu.h | 10 ++++++++++ > arch/aarch64/init.c | 22 ++++++++++++++++++++++ > 2 files changed, 32 insertions(+) > > diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h > index ce80b6e..49f5a71 100644 > --- a/arch/aarch64/include/asm/cpu.h > +++ b/arch/aarch64/include/asm/cpu.h > @@ -49,6 +49,7 @@ > #define SCR_EL3_FGTEN BIT(27) > #define SCR_EL3_ECVEN BIT(28) > #define SCR_EL3_TME BIT(34) > +#define SCR_EL3_EnTP2 BIT(41) > > #define HCR_EL2_RES1 BIT(1) > > @@ -69,9 +70,13 @@ > #define ID_AA64MMFR0_EL1_FGT BITS(59, 56) > #define ID_AA64MMFR0_EL1_ECV BITS(63, 60) > > +#define ID_AA64PFR1_EL1_SME BITS(27, 24) > #define ID_AA64PFR1_EL1_MTE BITS(11, 8) > #define ID_AA64PFR0_EL1_SVE BITS(35, 32) > > +#define ID_AA64SMFR0_EL1 s3_0_c0_c4_5 > +#define ID_AA64SMFR0_EL1_FA64 (1UL << 63) For consistency with the other ID fields, I'm going to make this: #define ID_AA64SMFR0_EL1_FA64 BIT(63) In future I'd like to split the remaining definitions using shifted bits into separate _ and __ definitions (or something of that rought shape) so that field boundaries are always explicit, but those can stay as-is for now. > + > /* > * Initial register values required for the boot-wrapper to run out-of-reset. > */ > @@ -96,6 +101,7 @@ > #define SPSR_EL2H (9 << 0) /* EL2 Handler mode */ > #define SPSR_HYP (0x1a << 0) /* M[3:0] = hyp, M[4] = AArch32 */ > > +#define CPTR_EL3_ESM (1 << 12) > #define CPTR_EL3_EZ (1 << 8) > > #define ICC_SRE_EL2 S3_4_C12_C9_5 > @@ -107,6 +113,10 @@ > #define ZCR_EL3 s3_6_c1_c2_0 > #define ZCR_EL3_LEN_MAX 0xf > > +#define SMCR_EL3 s3_6_c1_c2_6 > +#define SMCR_EL3_FA64 (1 << 31) > +#define SMCR_EL3_LEN_MAX 0xf > + > #define ID_AA64ISAR2_EL1 s3_0_c0_c6_2 > > #define SCTLR_EL1_CP15BEN (1 << 5) > diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c > index 8bb0524..db73b58 100644 > --- a/arch/aarch64/init.c > +++ b/arch/aarch64/init.c > @@ -47,6 +47,7 @@ void cpu_init_el3(void) > unsigned long scr = SCR_EL3_RES1 | SCR_EL3_NS | SCR_EL3_HCE; > unsigned long mdcr = 0; > unsigned long cptr = 0; > + unsigned long smcr = 0; > > if (cpu_has_pauth()) > scr |= SCR_EL3_APK | SCR_EL3_API; > @@ -95,6 +96,27 @@ void cpu_init_el3(void) > msr(ZCR_EL3, ZCR_EL3_LEN_MAX); > } > > + if (mrs_field(ID_AA64PFR1_EL1, SME)) { > + cptr |= CPTR_EL3_ESM; > + msr(CPTR_EL3, cptr); > + isb(); > + > + scr |= SCR_EL3_EnTP2; > + msr(SCR_EL3, scr); > + isb(); > + > + /* > + * Write the maximum possible vector length, hardware > + * will constrain to the actual limit. > + */ > + smcr = SMCR_EL3_LEN_MAX; > + > + if (mrs_field(ID_AA64SMFR0_EL1, FA64)) > + smcr |= SMCR_EL3_FA64; > + > + msr(SMCR_EL3, smcr); > + } > + > msr(CNTFRQ_EL0, COUNTER_FREQ); > } > > -- > 2.30.2 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel