[PATCH V2 0/4] crypto: Add Xilinx ZynqMP SHA3 driver support

[PATCH V2 0/4] crypto: Add Xilinx ZynqMP SHA3 driver support

[Harsha]

This patch set does the following:
  - Updates the Makefile for xilinx subdirectory
  - Adds communication layer support for sha_hash in zynqmp.c
  - Adds Xilinx ZynqMP driver for SHA3 Algorithm
  - Updates the list of MAINTAINERS

V2 changes:
- Removed dependency on COMPILE_TEST in 3/4
- Rebased this patchset on latest Cryptodev-2.6 tree which fixed
below kernel robot warning
   In file included from ./arch/s390/include/generated/asm/cacheflush.h:1,
                    from drivers/crypto/xilinx/zynqmp-sha.c:6:
include/asm-generic/cacheflush.h:53:46: warning: 'struct folio' declared
inside parameter list will not be visible outside of this definition
or declaration
      53 | static inline void flush_dcache_folio(struct folio *folio) { }
         |
- Included linux/cacheflush.h instead of asm/cacheflush.h in 3/4
 

V1 changes:
- Converted RFC patch to PATCH
- Updated zynqmp-sha driver so that it can be self discovered 
- Removed patch 3/6 and 4/6 as they added support for device tree
- Substituted hw with hardware in drivers/crypto/Kconfig

Harsha (4):
  drivers: crypto: Updated Makefile for xilinx subdirectory
  firmware: xilinx: Add ZynqMP SHA API for SHA3 functionality
  crypto: xilinx: Add Xilinx SHA3 driver
  MAINTAINERS: Add maintainer for Xilinx ZynqMP SHA3 driver

 MAINTAINERS                          |   5 +
 drivers/crypto/Kconfig               |  10 ++
 drivers/crypto/Makefile              |   2 +-
 drivers/crypto/xilinx/Makefile       |   1 +
 drivers/crypto/xilinx/zynqmp-sha.c   | 285 +++++++++++++++++++++++++++++++++++
 drivers/firmware/xilinx/zynqmp.c     |  26 ++++
 include/linux/firmware/xlnx-zynqmp.h |   8 +
 7 files changed, 336 insertions(+), 1 deletion(-)
 create mode 100644 drivers/crypto/xilinx/zynqmp-sha.c

-- 
1.8.2.1


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[PATCH V2 1/4] drivers: crypto: Updated Makefile for xilinx subdirectory

[Harsha]

This patch updates the Makefile for xilinx subdirectory.
CONFIG_CRYPTO_DEV_ZYNQMP_AES protects zynqmp-aes-gcm.o and it is used
twice (in drivers/crypto/Makefile and drivers/crypto/xilinx/Makefile)
and it is enough to use it once.

Signed-off-by: Harsha <harsha.harsha@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
---
 drivers/crypto/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 1fe5120..0a4fff2 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -47,7 +47,7 @@ obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
 obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/
 obj-$(CONFIG_CRYPTO_DEV_SAFEXCEL) += inside-secure/
 obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) += axis/
-obj-$(CONFIG_CRYPTO_DEV_ZYNQMP_AES) += xilinx/
+obj-y += xilinx/
 obj-y += hisilicon/
 obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) += amlogic/
 obj-y += keembay/
-- 
1.8.2.1


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[PATCH V2 2/4] firmware: xilinx: Add ZynqMP SHA API for SHA3 functionality

[Harsha]

This patch adds zynqmp_pm_sha_hash API in the ZynqMP firmware to compute
SHA3 hash of given data.

Signed-off-by: Harsha <harsha.harsha@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
---
 drivers/firmware/xilinx/zynqmp.c     | 26 ++++++++++++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h |  8 ++++++++
 2 files changed, 34 insertions(+)

diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 450c5f6..5e5b0bb 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -1121,6 +1121,32 @@ int zynqmp_pm_aes_engine(const u64 address, u32 *out)
 EXPORT_SYMBOL_GPL(zynqmp_pm_aes_engine);
 
 /**
+ * zynqmp_pm_sha_hash - Access the SHA engine to calculate the hash
+ * @address:	Address of the data/ Address of output buffer where
+ *		hash should be stored.
+ * @size:	Size of the data.
+ * @flags:
+ *	BIT(0) - for initializing csudma driver and SHA3(Here address
+ *		 and size inputs can be NULL).
+ *	BIT(1) - to call Sha3_Update API which can be called multiple
+ *		 times when data is not contiguous.
+ *	BIT(2) - to get final hash of the whole updated data.
+ *		 Hash will be overwritten at provided address with
+ *		 48 bytes.
+ *
+ * Return:	Returns status, either success or error code.
+ */
+int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags)
+{
+	u32 lower_addr = lower_32_bits(address);
+	u32 upper_addr = upper_32_bits(address);
+
+	return zynqmp_pm_invoke_fn(PM_SECURE_SHA, upper_addr, lower_addr,
+				   size, flags, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_sha_hash);
+
+/**
  * zynqmp_pm_register_notifier() - PM API for register a subsystem
  *                                to be notified about specific
  *                                event/error.
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 907cb01..f6783f5 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -93,6 +93,7 @@ enum pm_api_id {
 	PM_FPGA_LOAD = 22,
 	PM_FPGA_GET_STATUS = 23,
 	PM_GET_CHIPID = 24,
+	PM_SECURE_SHA = 26,
 	PM_PINCTRL_REQUEST = 28,
 	PM_PINCTRL_RELEASE = 29,
 	PM_PINCTRL_GET_FUNCTION = 30,
@@ -427,6 +428,7 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
 			      const u32 qos,
 			      const enum zynqmp_pm_request_ack ack);
 int zynqmp_pm_aes_engine(const u64 address, u32 *out);
+int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);
 int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
 int zynqmp_pm_fpga_get_status(u32 *value);
 int zynqmp_pm_write_ggs(u32 index, u32 value);
@@ -601,6 +603,12 @@ static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
 	return -ENODEV;
 }
 
+static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size,
+				     const u32 flags)
+{
+	return -ENODEV;
+}
+
 static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
 				      const u32 flags)
 {
-- 
1.8.2.1


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Re: [PATCH V2 2/4] firmware: xilinx: Add ZynqMP SHA API for SHA3 functionality

[Corentin Labbe]

Le Fri, Feb 18, 2022 at 12:44:22AM +0530, Harsha a écrit :
> This patch adds zynqmp_pm_sha_hash API in the ZynqMP firmware to compute
> SHA3 hash of given data.
> 
> Signed-off-by: Harsha <harsha.harsha@xilinx.com>
> Acked-by: Michal Simek <michal.simek@xilinx.com>
> ---

Hello

Your signed-off should contain your real name.
Furthermore why did you drop copyright from previous poster ?
See https://patchwork.kernel.org/project/linux-crypto/cover/1556793282-17346-1-git-send-email-kalyani.akula@xilinx.com/ for reference.

Furthermore, the previous poster didnt answered my questions about parallel processing and tests.

Regards

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RE: [PATCH V2 2/4] firmware: xilinx: Add ZynqMP SHA API for SHA3 functionality

[Harsha Harsha]

> -----Original Message-----
> From: Corentin Labbe <clabbe.montjoie@gmail.com>
> Sent: Friday, February 18, 2022 3:13 PM
> To: Harsha Harsha <harshah@xilinx.com>
> Cc: herbert@gondor.apana.org.au; davem@davemloft.net; linux-crypto@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; Michal Simek <michals@xilinx.com>; Sarat Chand Savitala <saratcha@xilinx.com>; Harsh Jain
> <harshj@xilinx.com>; git <git@xilinx.com>
> Subject: Re: [PATCH V2 2/4] firmware: xilinx: Add ZynqMP SHA API for SHA3 functionality
> 
> Le Fri, Feb 18, 2022 at 12:44:22AM +0530, Harsha a écrit :
> > This patch adds zynqmp_pm_sha_hash API in the ZynqMP firmware to compute
> > SHA3 hash of given data.
> >
> > Signed-off-by: Harsha <harsha.harsha@xilinx.com>
> > Acked-by: Michal Simek <michal.simek@xilinx.com>
> > ---
> 
> Hello
> 
> Your signed-off should contain your real name.

My complete name is Harsha which I have mentioned in the signed-off section.

> Furthermore why did you drop copyright from previous poster ?
> See https://patchwork.kernel.org/project/linux-crypto/cover/1556793282-17346-1-git-send-email-kalyani.akula@xilinx.com/ for
> reference.

I did not understand the comment. Do you want me to add Kalyani's name also in the Signed of section?

> 
> Furthermore, the previous poster didnt answered my questions about parallel processing and tests.

Since SHA3 HW engine in ZynqMPSoC does not support parallel processing of 2 hash requests, so we have changed our approach. 
Now  to support parallel processing of 2 hash requests, software fallback is being used for init, update, final, export and import in the ZynqMP SHA driver.
For digest, the calculation of SHA3 hash is done by the hardened SHA3 accelerator in Xilinx ZynqMP SoC.

Following tests have been done for the driver:
- Enabled kernel self tests and extra run-time crypto self tests
- Tested SHA hash computation for different sizes of data using userspace application
- Tested SHA hash computation using multiple updates of data using userspace application
- Tested parallel hash computation
- Tested using the tcrypt module

> 
> Regards

Regards,
Harsha

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RE: [PATCH V2 2/4] firmware: xilinx: Add ZynqMP SHA API for SHA3 functionality

[Harsha Harsha]

> -----Original Message-----
> From: Harsha Harsha
> Sent: Monday, February 21, 2022 5:47 PM
> To: Corentin Labbe <clabbe.montjoie@gmail.com>
> Cc: herbert@gondor.apana.org.au; davem@davemloft.net; linux-crypto@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; Michal Simek <michals@xilinx.com>; Sarat Chand Savitala <saratcha@xilinx.com>; Harsh Jain
> <harshj@xilinx.com>; git <git@xilinx.com>
> Subject: RE: [PATCH V2 2/4] firmware: xilinx: Add ZynqMP SHA API for SHA3 functionality
> 
> 
> 
> > -----Original Message-----
> > From: Corentin Labbe <clabbe.montjoie@gmail.com>
> > Sent: Friday, February 18, 2022 3:13 PM
> > To: Harsha Harsha <harshah@xilinx.com>
> > Cc: herbert@gondor.apana.org.au; davem@davemloft.net; linux-crypto@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> > kernel@lists.infradead.org; Michal Simek <michals@xilinx.com>; Sarat Chand Savitala <saratcha@xilinx.com>; Harsh Jain
> > <harshj@xilinx.com>; git <git@xilinx.com>
> > Subject: Re: [PATCH V2 2/4] firmware: xilinx: Add ZynqMP SHA API for SHA3 functionality
> >
> > Le Fri, Feb 18, 2022 at 12:44:22AM +0530, Harsha a écrit :
> > > This patch adds zynqmp_pm_sha_hash API in the ZynqMP firmware to compute
> > > SHA3 hash of given data.
> > >
> > > Signed-off-by: Harsha <harsha.harsha@xilinx.com>
> > > Acked-by: Michal Simek <michal.simek@xilinx.com>
> > > ---
> >
> > Hello
> >
> > Your signed-off should contain your real name.
> 
> My complete name is Harsha which I have mentioned in the signed-off section.

I shall update SOB as Signed-off-by: Harsha Harsha <harsha.harsha@xilinx.com> in the next version of patch.

> 
> > Furthermore why did you drop copyright from previous poster ?
> > See https://patchwork.kernel.org/project/linux-crypto/cover/1556793282-17346-1-git-send-email-kalyani.akula@xilinx.com/ for
> > reference.
> 
> I did not understand the comment. Do you want me to add Kalyani's name also in the Signed of section?

I will retain Kalyani as the author in next version of patch.

> 
> >
> > Furthermore, the previous poster didnt answered my questions about parallel processing and tests.
> 
> Since SHA3 HW engine in ZynqMPSoC does not support parallel processing of 2 hash requests, so we have changed our approach.
> Now  to support parallel processing of 2 hash requests, software fallback is being used for init, update, final, export and import in the
> ZynqMP SHA driver.
> For digest, the calculation of SHA3 hash is done by the hardened SHA3 accelerator in Xilinx ZynqMP SoC.
> 
> Following tests have been done for the driver:
> - Enabled kernel self tests and extra run-time crypto self tests
> - Tested SHA hash computation for different sizes of data using userspace application
> - Tested SHA hash computation using multiple updates of data using userspace application
> - Tested parallel hash computation
> - Tested using the tcrypt module
> 
> >
> > Regards
> 
> Regards,
> Harsha

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Re: [PATCH V2 2/4] firmware: xilinx: Add ZynqMP SHA API for SHA3 functionality

[Corentin Labbe]

Le Mon, Feb 21, 2022 at 12:17:02PM +0000, Harsha Harsha a écrit :
> 
> 
> > -----Original Message-----
> > From: Corentin Labbe <clabbe.montjoie@gmail.com>
> > Sent: Friday, February 18, 2022 3:13 PM
> > To: Harsha Harsha <harshah@xilinx.com>
> > Cc: herbert@gondor.apana.org.au; davem@davemloft.net; linux-crypto@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> > kernel@lists.infradead.org; Michal Simek <michals@xilinx.com>; Sarat Chand Savitala <saratcha@xilinx.com>; Harsh Jain
> > <harshj@xilinx.com>; git <git@xilinx.com>
> > Subject: Re: [PATCH V2 2/4] firmware: xilinx: Add ZynqMP SHA API for SHA3 functionality
> > 
> > Le Fri, Feb 18, 2022 at 12:44:22AM +0530, Harsha a écrit :
> > > This patch adds zynqmp_pm_sha_hash API in the ZynqMP firmware to compute
> > > SHA3 hash of given data.
> > >
> > > Signed-off-by: Harsha <harsha.harsha@xilinx.com>
> > > Acked-by: Michal Simek <michal.simek@xilinx.com>
> > > ---
> > 
> > Hello
> > 
> > Your signed-off should contain your real name.
> 
> My complete name is Harsha which I have mentioned in the signed-off section.

I am sorry, I believed it was your pseudo. If it is your real name, no change are needed.

> 
> > Furthermore why did you drop copyright from previous poster ?
> > See https://patchwork.kernel.org/project/linux-crypto/cover/1556793282-17346-1-git-send-email-kalyani.akula@xilinx.com/ for
> > reference.
> 
> I did not understand the comment. Do you want me to add Kalyani's name also in the Signed of section?
> 
> > 
> > Furthermore, the previous poster didnt answered my questions about parallel processing and tests.
> 
> Since SHA3 HW engine in ZynqMPSoC does not support parallel processing of 2 hash requests, so we have changed our approach. 
> Now  to support parallel processing of 2 hash requests, software fallback is being used for init, update, final, export and import in the ZynqMP SHA driver.
> For digest, the calculation of SHA3 hash is done by the hardened SHA3 accelerator in Xilinx ZynqMP SoC.
> 

I asked for parallel processing since I didnt see any locking or way to prevent hardware to be used in the same time.
But the final work is done by a firmware call, so my knowledge stop here.

> Following tests have been done for the driver:
> - Enabled kernel self tests and extra run-time crypto self tests
> - Tested SHA hash computation for different sizes of data using userspace application
> - Tested SHA hash computation using multiple updates of data using userspace application
> - Tested parallel hash computation
> - Tested using the tcrypt module
> 

This should be in the cover letter.

Regards

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[PATCH V2 3/4] crypto: xilinx: Add Xilinx SHA3 driver

[Harsha]

This patch adds SHA3 driver support for the Xilinx ZynqMP SoC.
Xilinx ZynqMP SoC has SHA3 engine used for secure hash calculation.
The flow is
SHA3 request from Userspace -> SHA3 driver-> ZynqMp driver-> Firmware ->
SHA3 HW Engine

SHA3 HW engine in Xilinx ZynqMP SoC, does not support parallel processing
of 2 hash requests.
Therefore, software fallback is being used for init, update, final,
export and import in the ZynqMP SHA driver
For digest, the calculation of SHA3 hash is done by the hardened
SHA3 accelerator in Xilinx ZynqMP SoC.

Signed-off-by: Harsha <harsha.harsha@xilinx.com>
---
 drivers/crypto/Kconfig             |  10 ++
 drivers/crypto/xilinx/Makefile     |   1 +
 drivers/crypto/xilinx/zynqmp-sha.c | 285 +++++++++++++++++++++++++++++++++++++
 3 files changed, 296 insertions(+)
 create mode 100644 drivers/crypto/xilinx/zynqmp-sha.c

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 4f70567..bf4e55e 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -808,6 +808,16 @@ config CRYPTO_DEV_ZYNQMP_AES
 	  accelerator. Select this if you want to use the ZynqMP module
 	  for AES algorithms.
 
+config CRYPTO_DEV_ZYNQMP_SHA3
+	bool "Support for Xilinx ZynqMP SHA3 hardware accelerator"
+	depends on ARCH_ZYNQMP
+	select CRYPTO_SHA3
+	help
+	  Xilinx ZynqMP has SHA3 engine used for secure hash calculation.
+	  This driver interfaces with SHA3 hardware engine.
+	  Select this if you want to use the ZynqMP module
+	  for SHA3 hash computation.
+
 source "drivers/crypto/chelsio/Kconfig"
 
 source "drivers/crypto/virtio/Kconfig"
diff --git a/drivers/crypto/xilinx/Makefile b/drivers/crypto/xilinx/Makefile
index 534e32d..730feff 100644
--- a/drivers/crypto/xilinx/Makefile
+++ b/drivers/crypto/xilinx/Makefile
@@ -1,2 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0-only
 obj-$(CONFIG_CRYPTO_DEV_ZYNQMP_AES) += zynqmp-aes-gcm.o
+obj-$(CONFIG_CRYPTO_DEV_ZYNQMP_SHA3) += zynqmp-sha.o
diff --git a/drivers/crypto/xilinx/zynqmp-sha.c b/drivers/crypto/xilinx/zynqmp-sha.c
new file mode 100644
index 0000000..1eaca97
--- /dev/null
+++ b/drivers/crypto/xilinx/zynqmp-sha.c
@@ -0,0 +1,285 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx ZynqMP SHA Driver.
+ * Copyright (c) 2022 Xilinx Inc.
+ */
+#include <linux/cacheflush.h>
+#include <crypto/hash.h>
+#include <crypto/internal/hash.h>
+#include <crypto/sha3.h>
+#include <linux/crypto.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/firmware/xlnx-zynqmp.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#define ZYNQMP_DMA_BIT_MASK		32U
+#define ZYNQMP_DMA_ALLOC_FIXED_SIZE	0x1000U
+
+enum zynqmp_sha_op {
+	ZYNQMP_SHA3_INIT = 1,
+	ZYNQMP_SHA3_UPDATE = 2,
+	ZYNQMP_SHA3_FINAL = 4,
+};
+
+struct zynqmp_sha_drv_ctx {
+	struct shash_alg sha3_384;
+	struct device *dev;
+};
+
+struct zynqmp_sha_tfm_ctx {
+	struct device *dev;
+	struct crypto_shash *fbk_tfm;
+};
+
+struct zynqmp_sha_desc_ctx {
+	struct shash_desc fbk_req;
+};
+
+static dma_addr_t update_dma_addr, final_dma_addr;
+static char *ubuf, *fbuf;
+
+static int zynqmp_sha_init_tfm(struct crypto_shash *hash)
+{
+	const char *fallback_driver_name = crypto_shash_alg_name(hash);
+	struct zynqmp_sha_tfm_ctx *tfm_ctx = crypto_shash_ctx(hash);
+	struct shash_alg *alg = crypto_shash_alg(hash);
+	struct crypto_shash *fallback_tfm;
+	struct zynqmp_sha_drv_ctx *drv_ctx;
+
+	drv_ctx = container_of(alg, struct zynqmp_sha_drv_ctx, sha3_384);
+	tfm_ctx->dev = drv_ctx->dev;
+
+	/* Allocate a fallback and abort if it failed. */
+	fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0,
+					  CRYPTO_ALG_NEED_FALLBACK);
+	if (IS_ERR(fallback_tfm))
+		return PTR_ERR(fallback_tfm);
+
+	tfm_ctx->fbk_tfm = fallback_tfm;
+	hash->descsize += crypto_shash_descsize(tfm_ctx->fbk_tfm);
+
+	return 0;
+}
+
+static void zynqmp_sha_exit_tfm(struct crypto_shash *hash)
+{
+	struct zynqmp_sha_tfm_ctx *tfm_ctx = crypto_shash_ctx(hash);
+
+	if (tfm_ctx->fbk_tfm) {
+		crypto_free_shash(tfm_ctx->fbk_tfm);
+		tfm_ctx->fbk_tfm = NULL;
+	}
+
+	memzero_explicit(tfm_ctx, sizeof(struct zynqmp_sha_tfm_ctx));
+}
+
+static int zynqmp_sha_init(struct shash_desc *desc)
+{
+	struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
+	struct zynqmp_sha_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm);
+
+	dctx->fbk_req.tfm = tctx->fbk_tfm;
+	return crypto_shash_init(&dctx->fbk_req);
+}
+
+static int zynqmp_sha_update(struct shash_desc *desc, const u8 *data, unsigned int length)
+{
+	struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
+
+	return crypto_shash_update(&dctx->fbk_req, data, length);
+}
+
+static int zynqmp_sha_final(struct shash_desc *desc, u8 *out)
+{
+	struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
+
+	return crypto_shash_final(&dctx->fbk_req, out);
+}
+
+static int zynqmp_sha_finup(struct shash_desc *desc, const u8 *data, unsigned int length, u8 *out)
+{
+	struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
+
+	return crypto_shash_finup(&dctx->fbk_req, data, length, out);
+}
+
+static int zynqmp_sha_import(struct shash_desc *desc, const void *in)
+{
+	struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
+	struct zynqmp_sha_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm);
+
+	dctx->fbk_req.tfm = tctx->fbk_tfm;
+	return crypto_shash_import(&dctx->fbk_req, in);
+}
+
+static int zynqmp_sha_export(struct shash_desc *desc, void *out)
+{
+	struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
+
+	return crypto_shash_export(&dctx->fbk_req, out);
+}
+
+static int zynqmp_sha_digest(struct shash_desc *desc, const u8 *data, unsigned int len, u8 *out)
+{
+	unsigned int remaining_len = len;
+	int update_size;
+	int ret;
+
+	ret = zynqmp_pm_sha_hash(0, 0, ZYNQMP_SHA3_INIT);
+	if (ret)
+		return ret;
+
+	while (remaining_len != 0) {
+		memset(ubuf, 0, ZYNQMP_DMA_ALLOC_FIXED_SIZE);
+		if (remaining_len >= ZYNQMP_DMA_ALLOC_FIXED_SIZE) {
+			update_size = ZYNQMP_DMA_ALLOC_FIXED_SIZE;
+			remaining_len -= ZYNQMP_DMA_ALLOC_FIXED_SIZE;
+		} else {
+			update_size = remaining_len;
+			remaining_len = 0;
+		}
+		memcpy(ubuf, data, update_size);
+		flush_icache_range((unsigned long)ubuf, (unsigned long)ubuf + update_size);
+		ret = zynqmp_pm_sha_hash(update_dma_addr, update_size, ZYNQMP_SHA3_UPDATE);
+		if (ret)
+			return ret;
+
+		data += update_size;
+	}
+
+	ret = zynqmp_pm_sha_hash(final_dma_addr, SHA3_384_DIGEST_SIZE, ZYNQMP_SHA3_FINAL);
+	memcpy(out, fbuf, SHA3_384_DIGEST_SIZE);
+	memset(fbuf, 0, SHA3_384_DIGEST_SIZE);
+
+	return ret;
+}
+
+static struct zynqmp_sha_drv_ctx sha3_drv_ctx = {
+	.sha3_384 = {
+		.init = zynqmp_sha_init,
+		.update = zynqmp_sha_update,
+		.final = zynqmp_sha_final,
+		.finup = zynqmp_sha_finup,
+		.digest = zynqmp_sha_digest,
+		.export = zynqmp_sha_export,
+		.import = zynqmp_sha_import,
+		.init_tfm = zynqmp_sha_init_tfm,
+		.exit_tfm = zynqmp_sha_exit_tfm,
+		.descsize = sizeof(struct zynqmp_sha_desc_ctx),
+		.statesize = sizeof(struct sha3_state),
+		.digestsize = SHA3_384_DIGEST_SIZE,
+		.base = {
+			.cra_name = "sha3-384",
+			.cra_driver_name = "zynqmp-sha3-384",
+			.cra_priority = 300,
+			.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
+				     CRYPTO_ALG_ALLOCATES_MEMORY |
+				     CRYPTO_ALG_NEED_FALLBACK,
+			.cra_blocksize = SHA3_384_BLOCK_SIZE,
+			.cra_ctxsize = sizeof(struct zynqmp_sha_tfm_ctx),
+			.cra_alignmask = 3,
+			.cra_module = THIS_MODULE,
+		}
+	}
+};
+
+static int zynqmp_sha_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	int err;
+
+	err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(ZYNQMP_DMA_BIT_MASK));
+	if (err < 0) {
+		dev_err(dev, "No usable DMA configuration\n");
+		return err;
+	}
+
+	err = crypto_register_shash(&sha3_drv_ctx.sha3_384);
+	if (err < 0) {
+		dev_err(dev, "Failed to register shash alg.\n");
+		return err;
+	}
+
+	sha3_drv_ctx.dev = dev;
+	platform_set_drvdata(pdev, &sha3_drv_ctx);
+
+	ubuf = dma_alloc_coherent(dev, ZYNQMP_DMA_ALLOC_FIXED_SIZE, &update_dma_addr, GFP_KERNEL);
+	if (!ubuf) {
+		err = -ENOMEM;
+		goto err_shash;
+	}
+
+	fbuf = dma_alloc_coherent(dev, SHA3_384_DIGEST_SIZE, &final_dma_addr, GFP_KERNEL);
+	if (!fbuf) {
+		err = -ENOMEM;
+		goto err_mem;
+	}
+
+	return 0;
+
+err_mem:
+	dma_free_coherent(sha3_drv_ctx.dev, ZYNQMP_DMA_ALLOC_FIXED_SIZE, ubuf, update_dma_addr);
+
+err_shash:
+	crypto_unregister_shash(&sha3_drv_ctx.sha3_384);
+
+	return err;
+}
+
+static int zynqmp_sha_remove(struct platform_device *pdev)
+{
+	sha3_drv_ctx.dev = platform_get_drvdata(pdev);
+
+	dma_free_coherent(sha3_drv_ctx.dev, ZYNQMP_DMA_ALLOC_FIXED_SIZE, ubuf, update_dma_addr);
+	dma_free_coherent(sha3_drv_ctx.dev, SHA3_384_DIGEST_SIZE, fbuf, final_dma_addr);
+	crypto_unregister_shash(&sha3_drv_ctx.sha3_384);
+
+	return 0;
+}
+
+static struct platform_driver zynqmp_sha_driver = {
+	.probe = zynqmp_sha_probe,
+	.remove = zynqmp_sha_remove,
+	.driver = {
+		.name = "zynqmp-sha3-384",
+	},
+};
+
+static int __init sha_driver_init(void)
+{
+	struct platform_device *pdev;
+	int ret;
+
+	ret = platform_driver_register(&zynqmp_sha_driver);
+	if (ret)
+		return ret;
+
+	pdev = platform_device_register_simple(zynqmp_sha_driver.driver.name,
+					       0, NULL, 0);
+	if (IS_ERR(pdev)) {
+		ret = PTR_ERR(pdev);
+		platform_driver_unregister(&zynqmp_sha_driver);
+		pr_info("Failed to register ZynqMP SHA3 dvixe %d\n", ret);
+	}
+
+	return ret;
+}
+
+device_initcall(sha_driver_init);
+
+static void __exit sha_driver_exit(void)
+{
+	platform_driver_unregister(&zynqmp_sha_driver);
+}
+
+module_platform_driver(zynqmp_sha_driver);
+
+MODULE_DESCRIPTION("ZynqMP SHA3 hardware acceleration support.");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Harsha <harsha.harsha@xilinx.com>");
-- 
1.8.2.1


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Re: [PATCH V2 3/4] crypto: xilinx: Add Xilinx SHA3 driver

[Corentin Labbe]

Le Fri, Feb 18, 2022 at 12:44:23AM +0530, Harsha a écrit :
> This patch adds SHA3 driver support for the Xilinx ZynqMP SoC.
> Xilinx ZynqMP SoC has SHA3 engine used for secure hash calculation.
> The flow is
> SHA3 request from Userspace -> SHA3 driver-> ZynqMp driver-> Firmware ->
> SHA3 HW Engine
> 
> SHA3 HW engine in Xilinx ZynqMP SoC, does not support parallel processing
> of 2 hash requests.
> Therefore, software fallback is being used for init, update, final,
> export and import in the ZynqMP SHA driver
> For digest, the calculation of SHA3 hash is done by the hardened
> SHA3 accelerator in Xilinx ZynqMP SoC.
> 
> Signed-off-by: Harsha <harsha.harsha@xilinx.com>
> ---
>  drivers/crypto/Kconfig             |  10 ++
>  drivers/crypto/xilinx/Makefile     |   1 +
>  drivers/crypto/xilinx/zynqmp-sha.c | 285 +++++++++++++++++++++++++++++++++++++
>  3 files changed, 296 insertions(+)
>  create mode 100644 drivers/crypto/xilinx/zynqmp-sha.c
> 
> diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
> index 4f70567..bf4e55e 100644
> --- a/drivers/crypto/Kconfig
> +++ b/drivers/crypto/Kconfig
> @@ -808,6 +808,16 @@ config CRYPTO_DEV_ZYNQMP_AES
>  	  accelerator. Select this if you want to use the ZynqMP module
>  	  for AES algorithms.
>  
> +config CRYPTO_DEV_ZYNQMP_SHA3
> +	bool "Support for Xilinx ZynqMP SHA3 hardware accelerator"
> +	depends on ARCH_ZYNQMP
> +	select CRYPTO_SHA3
> +	help
> +	  Xilinx ZynqMP has SHA3 engine used for secure hash calculation.
> +	  This driver interfaces with SHA3 hardware engine.
> +	  Select this if you want to use the ZynqMP module
> +	  for SHA3 hash computation.
> +
>  source "drivers/crypto/chelsio/Kconfig"
>  
>  source "drivers/crypto/virtio/Kconfig"
> diff --git a/drivers/crypto/xilinx/Makefile b/drivers/crypto/xilinx/Makefile
> index 534e32d..730feff 100644
> --- a/drivers/crypto/xilinx/Makefile
> +++ b/drivers/crypto/xilinx/Makefile
> @@ -1,2 +1,3 @@
>  # SPDX-License-Identifier: GPL-2.0-only
>  obj-$(CONFIG_CRYPTO_DEV_ZYNQMP_AES) += zynqmp-aes-gcm.o
> +obj-$(CONFIG_CRYPTO_DEV_ZYNQMP_SHA3) += zynqmp-sha.o
> diff --git a/drivers/crypto/xilinx/zynqmp-sha.c b/drivers/crypto/xilinx/zynqmp-sha.c
> new file mode 100644
> index 0000000..1eaca97
> --- /dev/null
> +++ b/drivers/crypto/xilinx/zynqmp-sha.c
> @@ -0,0 +1,285 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Xilinx ZynqMP SHA Driver.
> + * Copyright (c) 2022 Xilinx Inc.
> + */
> +#include <linux/cacheflush.h>
> +#include <crypto/hash.h>
> +#include <crypto/internal/hash.h>
> +#include <crypto/sha3.h>
> +#include <linux/crypto.h>
> +#include <linux/device.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/firmware/xlnx-zynqmp.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +
> +#define ZYNQMP_DMA_BIT_MASK		32U
> +#define ZYNQMP_DMA_ALLOC_FIXED_SIZE	0x1000U
> +
> +enum zynqmp_sha_op {
> +	ZYNQMP_SHA3_INIT = 1,
> +	ZYNQMP_SHA3_UPDATE = 2,
> +	ZYNQMP_SHA3_FINAL = 4,
> +};
> +
> +struct zynqmp_sha_drv_ctx {
> +	struct shash_alg sha3_384;
> +	struct device *dev;
> +};
> +
> +struct zynqmp_sha_tfm_ctx {
> +	struct device *dev;
> +	struct crypto_shash *fbk_tfm;
> +};
> +
> +struct zynqmp_sha_desc_ctx {
> +	struct shash_desc fbk_req;
> +};
> +
> +static dma_addr_t update_dma_addr, final_dma_addr;
> +static char *ubuf, *fbuf;
> +
> +static int zynqmp_sha_init_tfm(struct crypto_shash *hash)
> +{
> +	const char *fallback_driver_name = crypto_shash_alg_name(hash);
> +	struct zynqmp_sha_tfm_ctx *tfm_ctx = crypto_shash_ctx(hash);
> +	struct shash_alg *alg = crypto_shash_alg(hash);
> +	struct crypto_shash *fallback_tfm;
> +	struct zynqmp_sha_drv_ctx *drv_ctx;
> +
> +	drv_ctx = container_of(alg, struct zynqmp_sha_drv_ctx, sha3_384);
> +	tfm_ctx->dev = drv_ctx->dev;
> +
> +	/* Allocate a fallback and abort if it failed. */
> +	fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0,
> +					  CRYPTO_ALG_NEED_FALLBACK);
> +	if (IS_ERR(fallback_tfm))
> +		return PTR_ERR(fallback_tfm);
> +
> +	tfm_ctx->fbk_tfm = fallback_tfm;
> +	hash->descsize += crypto_shash_descsize(tfm_ctx->fbk_tfm);
> +
> +	return 0;
> +}
> +
> +static void zynqmp_sha_exit_tfm(struct crypto_shash *hash)
> +{
> +	struct zynqmp_sha_tfm_ctx *tfm_ctx = crypto_shash_ctx(hash);
> +
> +	if (tfm_ctx->fbk_tfm) {
> +		crypto_free_shash(tfm_ctx->fbk_tfm);
> +		tfm_ctx->fbk_tfm = NULL;
> +	}
> +
> +	memzero_explicit(tfm_ctx, sizeof(struct zynqmp_sha_tfm_ctx));
> +}
> +
> +static int zynqmp_sha_init(struct shash_desc *desc)
> +{
> +	struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
> +	struct zynqmp_sha_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm);
> +
> +	dctx->fbk_req.tfm = tctx->fbk_tfm;
> +	return crypto_shash_init(&dctx->fbk_req);
> +}
> +
> +static int zynqmp_sha_update(struct shash_desc *desc, const u8 *data, unsigned int length)
> +{
> +	struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
> +
> +	return crypto_shash_update(&dctx->fbk_req, data, length);
> +}
> +
> +static int zynqmp_sha_final(struct shash_desc *desc, u8 *out)
> +{
> +	struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
> +
> +	return crypto_shash_final(&dctx->fbk_req, out);
> +}
> +
> +static int zynqmp_sha_finup(struct shash_desc *desc, const u8 *data, unsigned int length, u8 *out)
> +{
> +	struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
> +
> +	return crypto_shash_finup(&dctx->fbk_req, data, length, out);
> +}
> +
> +static int zynqmp_sha_import(struct shash_desc *desc, const void *in)
> +{
> +	struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
> +	struct zynqmp_sha_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm);
> +
> +	dctx->fbk_req.tfm = tctx->fbk_tfm;
> +	return crypto_shash_import(&dctx->fbk_req, in);
> +}
> +
> +static int zynqmp_sha_export(struct shash_desc *desc, void *out)
> +{
> +	struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
> +
> +	return crypto_shash_export(&dctx->fbk_req, out);
> +}
> +
> +static int zynqmp_sha_digest(struct shash_desc *desc, const u8 *data, unsigned int len, u8 *out)
> +{
> +	unsigned int remaining_len = len;
> +	int update_size;
> +	int ret;
> +
> +	ret = zynqmp_pm_sha_hash(0, 0, ZYNQMP_SHA3_INIT);
> +	if (ret)
> +		return ret;
> +
> +	while (remaining_len != 0) {
> +		memset(ubuf, 0, ZYNQMP_DMA_ALLOC_FIXED_SIZE);
> +		if (remaining_len >= ZYNQMP_DMA_ALLOC_FIXED_SIZE) {
> +			update_size = ZYNQMP_DMA_ALLOC_FIXED_SIZE;
> +			remaining_len -= ZYNQMP_DMA_ALLOC_FIXED_SIZE;
> +		} else {
> +			update_size = remaining_len;
> +			remaining_len = 0;
> +		}
> +		memcpy(ubuf, data, update_size);
> +		flush_icache_range((unsigned long)ubuf, (unsigned long)ubuf + update_size);

Hello

Why do you copy all data before processing and not use them in-place ?


> +		ret = zynqmp_pm_sha_hash(update_dma_addr, update_size, ZYNQMP_SHA3_UPDATE);
> +		if (ret)
> +			return ret;
> +
> +		data += update_size;
> +	}
> +
> +	ret = zynqmp_pm_sha_hash(final_dma_addr, SHA3_384_DIGEST_SIZE, ZYNQMP_SHA3_FINAL);
> +	memcpy(out, fbuf, SHA3_384_DIGEST_SIZE);
> +	memset(fbuf, 0, SHA3_384_DIGEST_SIZE);

You should use memzero_explicit()

Regards

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RE: [PATCH V2 3/4] crypto: xilinx: Add Xilinx SHA3 driver

[Harsha Harsha]

> -----Original Message-----
> From: Corentin Labbe <clabbe.montjoie@gmail.com>
> Sent: Tuesday, February 22, 2022 3:32 PM
> To: Harsha Harsha <harshah@xilinx.com>
> Cc: herbert@gondor.apana.org.au; davem@davemloft.net; linux-crypto@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; Michal Simek <michals@xilinx.com>; Sarat Chand Savitala <saratcha@xilinx.com>; Harsh Jain
> <harshj@xilinx.com>; git <git@xilinx.com>
> Subject: Re: [PATCH V2 3/4] crypto: xilinx: Add Xilinx SHA3 driver
> 
> Le Fri, Feb 18, 2022 at 12:44:23AM +0530, Harsha a écrit :
> > This patch adds SHA3 driver support for the Xilinx ZynqMP SoC.
> > Xilinx ZynqMP SoC has SHA3 engine used for secure hash calculation.
> > The flow is
> > SHA3 request from Userspace -> SHA3 driver-> ZynqMp driver-> Firmware ->
> > SHA3 HW Engine
> >
> > SHA3 HW engine in Xilinx ZynqMP SoC, does not support parallel processing
> > of 2 hash requests.
> > Therefore, software fallback is being used for init, update, final,
> > export and import in the ZynqMP SHA driver
> > For digest, the calculation of SHA3 hash is done by the hardened
> > SHA3 accelerator in Xilinx ZynqMP SoC.
> >
> > Signed-off-by: Harsha <harsha.harsha@xilinx.com>
> > ---
> >  drivers/crypto/Kconfig             |  10 ++
> >  drivers/crypto/xilinx/Makefile     |   1 +
> >  drivers/crypto/xilinx/zynqmp-sha.c | 285 +++++++++++++++++++++++++++++++++++++
> >  3 files changed, 296 insertions(+)
> >  create mode 100644 drivers/crypto/xilinx/zynqmp-sha.c
> >
> > diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
> > index 4f70567..bf4e55e 100644
> > --- a/drivers/crypto/Kconfig
> > +++ b/drivers/crypto/Kconfig
> > @@ -808,6 +808,16 @@ config CRYPTO_DEV_ZYNQMP_AES
> >  	  accelerator. Select this if you want to use the ZynqMP module
> >  	  for AES algorithms.
> >
> > +config CRYPTO_DEV_ZYNQMP_SHA3
> > +	bool "Support for Xilinx ZynqMP SHA3 hardware accelerator"
> > +	depends on ARCH_ZYNQMP
> > +	select CRYPTO_SHA3
> > +	help
> > +	  Xilinx ZynqMP has SHA3 engine used for secure hash calculation.
> > +	  This driver interfaces with SHA3 hardware engine.
> > +	  Select this if you want to use the ZynqMP module
> > +	  for SHA3 hash computation.
> > +
> >  source "drivers/crypto/chelsio/Kconfig"
> >
> >  source "drivers/crypto/virtio/Kconfig"
> > diff --git a/drivers/crypto/xilinx/Makefile b/drivers/crypto/xilinx/Makefile
> > index 534e32d..730feff 100644
> > --- a/drivers/crypto/xilinx/Makefile
> > +++ b/drivers/crypto/xilinx/Makefile
> > @@ -1,2 +1,3 @@
> >  # SPDX-License-Identifier: GPL-2.0-only
> >  obj-$(CONFIG_CRYPTO_DEV_ZYNQMP_AES) += zynqmp-aes-gcm.o
> > +obj-$(CONFIG_CRYPTO_DEV_ZYNQMP_SHA3) += zynqmp-sha.o
> > diff --git a/drivers/crypto/xilinx/zynqmp-sha.c b/drivers/crypto/xilinx/zynqmp-sha.c
> > new file mode 100644
> > index 0000000..1eaca97
> > --- /dev/null
> > +++ b/drivers/crypto/xilinx/zynqmp-sha.c
> > @@ -0,0 +1,285 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Xilinx ZynqMP SHA Driver.
> > + * Copyright (c) 2022 Xilinx Inc.
> > + */
> > +#include <linux/cacheflush.h>
> > +#include <crypto/hash.h>
> > +#include <crypto/internal/hash.h>
> > +#include <crypto/sha3.h>
> > +#include <linux/crypto.h>
> > +#include <linux/device.h>
> > +#include <linux/dma-mapping.h>
> > +#include <linux/firmware/xlnx-zynqmp.h>
> > +#include <linux/init.h>
> > +#include <linux/io.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +
> > +#define ZYNQMP_DMA_BIT_MASK		32U
> > +#define ZYNQMP_DMA_ALLOC_FIXED_SIZE	0x1000U
> > +
> > +enum zynqmp_sha_op {
> > +	ZYNQMP_SHA3_INIT = 1,
> > +	ZYNQMP_SHA3_UPDATE = 2,
> > +	ZYNQMP_SHA3_FINAL = 4,
> > +};
> > +
> > +struct zynqmp_sha_drv_ctx {
> > +	struct shash_alg sha3_384;
> > +	struct device *dev;
> > +};
> > +
> > +struct zynqmp_sha_tfm_ctx {
> > +	struct device *dev;
> > +	struct crypto_shash *fbk_tfm;
> > +};
> > +
> > +struct zynqmp_sha_desc_ctx {
> > +	struct shash_desc fbk_req;
> > +};
> > +
> > +static dma_addr_t update_dma_addr, final_dma_addr;
> > +static char *ubuf, *fbuf;
> > +
> > +static int zynqmp_sha_init_tfm(struct crypto_shash *hash)
> > +{
> > +	const char *fallback_driver_name = crypto_shash_alg_name(hash);
> > +	struct zynqmp_sha_tfm_ctx *tfm_ctx = crypto_shash_ctx(hash);
> > +	struct shash_alg *alg = crypto_shash_alg(hash);
> > +	struct crypto_shash *fallback_tfm;
> > +	struct zynqmp_sha_drv_ctx *drv_ctx;
> > +
> > +	drv_ctx = container_of(alg, struct zynqmp_sha_drv_ctx, sha3_384);
> > +	tfm_ctx->dev = drv_ctx->dev;
> > +
> > +	/* Allocate a fallback and abort if it failed. */
> > +	fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0,
> > +					  CRYPTO_ALG_NEED_FALLBACK);
> > +	if (IS_ERR(fallback_tfm))
> > +		return PTR_ERR(fallback_tfm);
> > +
> > +	tfm_ctx->fbk_tfm = fallback_tfm;
> > +	hash->descsize += crypto_shash_descsize(tfm_ctx->fbk_tfm);
> > +
> > +	return 0;
> > +}
> > +
> > +static void zynqmp_sha_exit_tfm(struct crypto_shash *hash)
> > +{
> > +	struct zynqmp_sha_tfm_ctx *tfm_ctx = crypto_shash_ctx(hash);
> > +
> > +	if (tfm_ctx->fbk_tfm) {
> > +		crypto_free_shash(tfm_ctx->fbk_tfm);
> > +		tfm_ctx->fbk_tfm = NULL;
> > +	}
> > +
> > +	memzero_explicit(tfm_ctx, sizeof(struct zynqmp_sha_tfm_ctx));
> > +}
> > +
> > +static int zynqmp_sha_init(struct shash_desc *desc)
> > +{
> > +	struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
> > +	struct zynqmp_sha_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm);
> > +
> > +	dctx->fbk_req.tfm = tctx->fbk_tfm;
> > +	return crypto_shash_init(&dctx->fbk_req);
> > +}
> > +
> > +static int zynqmp_sha_update(struct shash_desc *desc, const u8 *data, unsigned int length)
> > +{
> > +	struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
> > +
> > +	return crypto_shash_update(&dctx->fbk_req, data, length);
> > +}
> > +
> > +static int zynqmp_sha_final(struct shash_desc *desc, u8 *out)
> > +{
> > +	struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
> > +
> > +	return crypto_shash_final(&dctx->fbk_req, out);
> > +}
> > +
> > +static int zynqmp_sha_finup(struct shash_desc *desc, const u8 *data, unsigned int length, u8 *out)
> > +{
> > +	struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
> > +
> > +	return crypto_shash_finup(&dctx->fbk_req, data, length, out);
> > +}
> > +
> > +static int zynqmp_sha_import(struct shash_desc *desc, const void *in)
> > +{
> > +	struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
> > +	struct zynqmp_sha_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm);
> > +
> > +	dctx->fbk_req.tfm = tctx->fbk_tfm;
> > +	return crypto_shash_import(&dctx->fbk_req, in);
> > +}
> > +
> > +static int zynqmp_sha_export(struct shash_desc *desc, void *out)
> > +{
> > +	struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
> > +
> > +	return crypto_shash_export(&dctx->fbk_req, out);
> > +}
> > +
> > +static int zynqmp_sha_digest(struct shash_desc *desc, const u8 *data, unsigned int len, u8 *out)
> > +{
> > +	unsigned int remaining_len = len;
> > +	int update_size;
> > +	int ret;
> > +
> > +	ret = zynqmp_pm_sha_hash(0, 0, ZYNQMP_SHA3_INIT);
> > +	if (ret)
> > +		return ret;
> > +
> > +	while (remaining_len != 0) {
> > +		memset(ubuf, 0, ZYNQMP_DMA_ALLOC_FIXED_SIZE);
> > +		if (remaining_len >= ZYNQMP_DMA_ALLOC_FIXED_SIZE) {
> > +			update_size = ZYNQMP_DMA_ALLOC_FIXED_SIZE;
> > +			remaining_len -= ZYNQMP_DMA_ALLOC_FIXED_SIZE;
> > +		} else {
> > +			update_size = remaining_len;
> > +			remaining_len = 0;
> > +		}
> > +		memcpy(ubuf, data, update_size);
> > +		flush_icache_range((unsigned long)ubuf, (unsigned long)ubuf + update_size);
> 
> Hello
> 
> Why do you copy all data before processing and not use them in-place ?

The firmware expects a DMA capable memory in the lower-32 bit address space. This is the reason we cannot use the data in-place.
ubuf is a pointer to the allocated region (in the processor's virtual
address space) returned by dma_alloc_coherent(). The driver copies the data in ubuf and
passes the associated dma handle to the firmware. This is the reason we cannot use the data in-place.

> 
> 
> > +		ret = zynqmp_pm_sha_hash(update_dma_addr, update_size, ZYNQMP_SHA3_UPDATE);
> > +		if (ret)
> > +			return ret;
> > +
> > +		data += update_size;
> > +	}
> > +
> > +	ret = zynqmp_pm_sha_hash(final_dma_addr, SHA3_384_DIGEST_SIZE, ZYNQMP_SHA3_FINAL);
> > +	memcpy(out, fbuf, SHA3_384_DIGEST_SIZE);
> > +	memset(fbuf, 0, SHA3_384_DIGEST_SIZE);
> 
> You should use memzero_explicit()

I will fix this in next version of patch.

> 
> Regards

Regards,
Harsha

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[PATCH V2 4/4] MAINTAINERS: Add maintainer for Xilinx ZynqMP SHA3 driver

[Harsha]

This patch adds an entry for ZynqMP SHA3 driver in the list of
Maintainers.

Signed-off-by: Harsha <harsha.harsha@xilinx.com>
---
 MAINTAINERS | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index ea3e6c9..6ee2441 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21229,6 +21229,11 @@ T:	git https://github.com/Xilinx/linux-xlnx.git
 F:	Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
 F:	drivers/phy/xilinx/phy-zynqmp.c
 
+XILINX ZYNQMP SHA3 DRIVER
+M:	Harsha <harsha.harsha@xilinx.com>
+S:	Maintained
+F:	drivers/crypto/xilinx/zynqmp-sha.c
+
 XILINX EVENT MANAGEMENT DRIVER
 M:	Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
 S:	Maintained
-- 
1.8.2.1


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