From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1E231C433EF for ; Tue, 8 Feb 2022 15:36:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ZuuKUjfliLED+SQJUEoUPYMs0VKmJeBw3PqOdw1oCvE=; b=KXta/L/wU2+XYE +/yCsgK5eNdLRjrs7uQlLiVpPl6/YA+qg+DQaOYCDqLLZw6eamlvhlnZwhwmtQOYdWa3D02U80WRK oXLe+gnCIGkiaxl+CKLpykKsUmgO5xA1kEzhl0NAmN4z7dvVNCwqSi3NkKL++YCcMIts8ur7Xbc8/ izFTx4KPGh6zX1024s/D9v7+LNuP6aHwJQCwuEyC2peiZl01k1yA8qAE8MnbTYBCuzkbYQJYGCG5d x+WTgKMiD8RCzyXH9jiXdxdu0JXQ/snT7ljPtYU2sRqA8wAg33mqPSqoMi09REVo/7FjZNs276iJA cZ7BfU45/7l/XoBJ8ObQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nHSWC-00EWCv-K3; Tue, 08 Feb 2022 15:35:00 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nHSW9-00EWAS-1u for linux-arm-kernel@lists.infradead.org; Tue, 08 Feb 2022 15:34:58 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 28A122B; Tue, 8 Feb 2022 07:34:54 -0800 (PST) Received: from monolith.localdoman (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1959A3F73B; Tue, 8 Feb 2022 07:34:50 -0800 (PST) Date: Tue, 8 Feb 2022 15:35:06 +0000 From: Alexandru Elisei To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, Andre Przywara , Christoffer Dall , Jintack Lim , Haibo Xu , Ganapatrao Kulkarni , Chase Conklin , "Russell King (Oracle)" , James Morse , Suzuki K Poulose , karl.heubaum@oracle.com, mihai.carabas@oracle.com, miguel.luis@oracle.com, kernel-team@android.com Subject: Re: [PATCH v6 28/64] KVM: arm64: nv: Emulate EL12 register accesses from the virtual EL2 Message-ID: References: <20220128121912.509006-1-maz@kernel.org> <20220128121912.509006-29-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220128121912.509006-29-maz@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220208_073457_220047_D94F1D11 X-CRM114-Status: GOOD ( 21.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc, On Fri, Jan 28, 2022 at 12:18:36PM +0000, Marc Zyngier wrote: > From: Jintack Lim > > With HCR_EL2.NV bit set, accesses to EL12 registers in the virtual EL2 > trap to EL2. Handle those traps just like we do for EL1 registers. > > One exception is CNTKCTL_EL12. We don't trap on CNTKCTL_EL1 for non-VHE > virtual EL2 because we don't have to. However, accessing CNTKCTL_EL12 > will trap since it's one of the EL12 registers controlled by HCR_EL2.NV > bit. Therefore, add a handler for it and don't treat it as a > non-trap-registers when preparing a shadow context. > > These registers, being only a view on their EL1 counterpart, are > permanently hidden from userspace. > > Signed-off-by: Jintack Lim > [maz: EL12_REG(), register visibility] > Signed-off-by: Marc Zyngier > --- > arch/arm64/kvm/sys_regs.c | 37 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 0c9bbe5eee5e..697bf0bca550 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -1634,6 +1634,26 @@ static unsigned int el2_visibility(const struct kvm_vcpu *vcpu, > .val = v, \ > } > > +/* > + * EL{0,1}2 registers are the EL2 view on an EL0 or EL1 register when > + * HCR_EL2.E2H==1, and only in the sysreg table for convenience of > + * handling traps. Given that, they are always hidden from userspace. > + */ > +static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu, > + const struct sys_reg_desc *rd) > +{ > + return REG_HIDDEN_USER; > +} > + > +#define EL12_REG(name, acc, rst, v) { \ > + SYS_DESC(SYS_##name##_EL12), \ > + .access = acc, \ > + .reset = rst, \ > + .reg = name##_EL1, \ > + .val = v, \ > + .visibility = elx2_visibility, \ > +} > + > /* sys_reg_desc initialiser for known cpufeature ID registers */ > #define ID_SANITISED(name) { \ > SYS_DESC(SYS_##name), \ > @@ -2194,6 +2214,23 @@ static const struct sys_reg_desc sys_reg_descs[] = { > EL2_REG(CNTVOFF_EL2, access_rw, reset_val, 0), > EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0), > > + EL12_REG(SCTLR, access_vm_reg, reset_val, 0x00C50078), > + EL12_REG(CPACR, access_rw, reset_val, 0), > + EL12_REG(TTBR0, access_vm_reg, reset_unknown, 0), > + EL12_REG(TTBR1, access_vm_reg, reset_unknown, 0), > + EL12_REG(TCR, access_vm_reg, reset_val, 0), > + { SYS_DESC(SYS_SPSR_EL12), access_spsr}, > + { SYS_DESC(SYS_ELR_EL12), access_elr}, > + EL12_REG(AFSR0, access_vm_reg, reset_unknown, 0), > + EL12_REG(AFSR1, access_vm_reg, reset_unknown, 0), > + EL12_REG(ESR, access_vm_reg, reset_unknown, 0), > + EL12_REG(FAR, access_vm_reg, reset_unknown, 0), > + EL12_REG(MAIR, access_vm_reg, reset_unknown, 0), > + EL12_REG(AMAIR, access_vm_reg, reset_amair_el1, 0), > + EL12_REG(VBAR, access_rw, reset_val, 0), > + EL12_REG(CONTEXTIDR, access_vm_reg, reset_val, 0), > + EL12_REG(CNTKCTL, access_rw, reset_val, 0), Compared against Table D5-48 from ARM DDI 0487G.a (page D5-2768), everything looks correct to me: Reviewed-by: Alexandru Elisei Thanks, Alex > + > EL2_REG(SP_EL2, NULL, reset_unknown, 0), > }; > > -- > 2.30.2 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel