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[34.83.12.150]) by smtp.gmail.com with ESMTPSA id y18sm11758088pgh.67.2022.02.08.09.29.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Feb 2022 09:29:43 -0800 (PST) Date: Tue, 8 Feb 2022 09:29:39 -0800 From: Ricardo Koller To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, James Morse , Suzuki K Poulose , Alexandru Elisei , kernel-team@android.com Subject: Re: [PATCH] KVM: arm64: vgic: Read HW interrupt pending state from the HW Message-ID: References: <20220208123726.3604198-1-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220208123726.3604198-1-maz@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220208_092949_225264_FDA0B7AD X-CRM114-Status: GOOD ( 23.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Feb 08, 2022 at 12:37:26PM +0000, Marc Zyngier wrote: > It appears that a read access to GIC[DR]_I[CS]PENDRn doesn't always > result in the pending interrupts being accurately reported if they are > mapped to a HW interrupt. This is particularily visible when acking > the timer interrupt and reading the GICR_ISPENDR1 register immediately > after, for example (the interrupt appears as not-pending while it really > is...). > > This is because a HW interrupt has its 'active and pending state' kept > in the *physical* distributor, and not in the virtual one, as mandated > by the spec (this is what allows the direct deactivation). The virtual > distributor only caries the pending and active *states* (note the > plural, as these are two independent and non-overlapping states). > > Fix it by reading the HW state back, either from the timer itself or > from the distributor if necessary. > > Reported-by: Ricardo Koller > Signed-off-by: Marc Zyngier > --- > arch/arm64/kvm/vgic/vgic-mmio.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/kvm/vgic/vgic-mmio.c b/arch/arm64/kvm/vgic/vgic-mmio.c > index 7068da080799..49837d3a3ef5 100644 > --- a/arch/arm64/kvm/vgic/vgic-mmio.c > +++ b/arch/arm64/kvm/vgic/vgic-mmio.c > @@ -248,6 +248,8 @@ unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu, > IRQCHIP_STATE_PENDING, > &val); > WARN_RATELIMIT(err, "IRQ %d", irq->host_irq); > + } else if (vgic_irq_is_mapped_level(irq)) { > + val = vgic_get_phys_line_level(irq); > } else { > val = irq_is_pending(irq); > } > -- > 2.34.1 > Thanks Marc! Tested this fix with a selftest that we are planning to upstream soon. It fires and handles arch timer IRQs while checking the pending state along the way. Tested-by: Ricardo Koller Reviewed-by: Ricardo Koller _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel