From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 40D8BC433FE for ; Mon, 14 Feb 2022 14:58:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=goojOK4orjVzkwXV4fx8jej/f30SlC60McsP/yKtPAU=; b=p9hs1S3m0bNS+F nCAoByQcCfnWqT1IWmzYwu8UI0Y/t9BZ96QgtbCRSI8iAUfkryPgo9nQj3OANdfEe67CS7m86u9RB lorAYGgvi24ZWKrmMeYPSxhfTdSPYIhBBmPqBDhan6PWLoyeKl2T8OGb6jkLHV5S1lpWTtyE/+bsG HNx+trnGCeH2PjwAP2VtrJQFpwPEL7Uc78lnt+mpRdYlC74rz+P2/wk+nmVK/R+S+dPESaHzWDcsr jAB4f5Z0gUI4/cbx8Yj9ea1N3hYkkl4rKDY6QPmPJqAUrLgm2UyXX+PPK77MQ5pzoMTrYWS0CUDHG GdoISlSdZKqY6UzKiJ3Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nJcmc-00FjXL-EI; Mon, 14 Feb 2022 14:56:54 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nJcmZ-00FjX2-2g for linux-arm-kernel@lists.infradead.org; Mon, 14 Feb 2022 14:56:52 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B541E1063; Mon, 14 Feb 2022 06:56:48 -0800 (PST) Received: from FVFF77S0Q05N (unknown [10.57.86.129]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 08CED3F70D; Mon, 14 Feb 2022 06:56:47 -0800 (PST) Date: Mon, 14 Feb 2022 14:56:42 +0000 From: Mark Rutland To: Joakim Tjernlund , Marc Zyngier Cc: "linux-arm-kernel@lists.infradead.org" Subject: Re: Buggy branch in __init_el2_gicv3? Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220214_065651_204501_18B15912 X-CRM114-Status: GOOD ( 12.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Feb 14, 2022 at 12:34:12PM +0000, Joakim Tjernlund wrote: > In init_el2_state calls __init_el2_gicv3 which looks: > > /* GICv3 system register access */ > .macro __init_el2_gicv3 > mrs x0, id_aa64pfr0_el1 > ubfx x0, x0, #ID_AA64PFR0_GIC_SHIFT, #4 > cbz x0, .Lskip_gicv3_\@ > > mrs_s x0, SYS_ICC_SRE_EL2 > orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 > orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 > msr_s SYS_ICC_SRE_EL2, x0 > isb // Make sure SRE is now set > mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back, > tbz x0, #0, 1f > // tbz x0, #0, .Lskip_gicv3_\@ // and check that it sticks > msr_s SYS_ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults > .Lskip_gicv3_\@: > .endm > > Note the tbz x0, #0, 1f, this instruction causes my A53 CPU to jump far out of the macro and make the > CPU go into EL0, failing with an exception a bit later. I believe the 1f is a bug and if I replace it with > tbz x0, #0, .Lskip_gicv3_\@ > the CPU continue too boot. You're right, that should be targetting `.Lskip_gicv3_\@`. It looks like that was left behind in commit: 114945d84a30a5fe ("arm64: Fix labels in el2_setup macros") Marc? > Why this is trigged is still a mystery to me, any pointers welcome :) I believe this happens if EL3 has ICC_SRE_EL3.SRE == 0b0; in that case ICC_SRE_EL2.SRE is RAZ/WI. i.e. your EL3 firmware isn't using GICv3 and hasn't enabled it for lower ELs. Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel