From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A2A56C433F5 for ; Wed, 2 Mar 2022 11:54:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=jnUO/PPAgI/Cqih3Fl/4tiiqA+LWRtDYW+pjzA7Y4OA=; b=VuzZVCRpnLHq13 Jy9C8LWlxdbGtF9lmEkvB5xd7ynsxqBPFCoQoZ2oNMQBT9qteMo+sW7y8hau1jiRjGA9ZV5M4UQqV eOGqxhPOuha7QTo8UjSIT4vQ26Kd80brdlIdWltGqAtvgT/WcOsd8pyP8dX1jjGvmR7D/FU7sBuAZ YbJlfJJKv4m7T2cUi/jvBSROOmY/vzCehQG+ghJU9c+fXpiAtkLx0akibOnSJmNTmlA3gCby/FcWD o73ZrgYy3HXDV78xA7bmDUiECEqCd1i/eQ61kKyz9C02s/IvcjlS2xcsQK1M9308uAuwO9mt+XmPx m7AuGsek6XvT5WKOC6Hg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nPNXQ-002Y7h-Si; Wed, 02 Mar 2022 11:53:00 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nPNXM-002Y6D-ML for linux-arm-kernel@lists.infradead.org; Wed, 02 Mar 2022 11:52:58 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 1E2FF618A0; Wed, 2 Mar 2022 11:52:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EE279C004E1; Wed, 2 Mar 2022 11:52:52 +0000 (UTC) Date: Wed, 2 Mar 2022 11:52:49 +0000 From: Catalin Marinas To: Marc Zyngier Cc: Qian Cai , Mark Brown , Will Deacon , Shuah Khan , Shuah Khan , Basant Kumar Dwivedi , Luis Machado , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Alan Hayward , kvmarm@lists.cs.columbia.edu, Salil Akerkar Subject: Re: [PATCH v11 03/40] arm64: cpufeature: Always specify and use a field width for capabilities Message-ID: References: <20220207152109.197566-1-broonie@kernel.org> <20220207152109.197566-4-broonie@kernel.org> <878rts3bpi.wl-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <878rts3bpi.wl-maz@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220302_035256_795885_51B26C1D X-CRM114-Status: GOOD ( 23.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Mar 02, 2022 at 10:12:09AM +0000, Marc Zyngier wrote: > On Tue, 01 Mar 2022 22:56:41 +0000, > Qian Cai wrote: > > > > On Mon, Feb 07, 2022 at 03:20:32PM +0000, Mark Brown wrote: > > > Since all the fields in the main ID registers are 4 bits wide we have up > > > until now not bothered specifying the width in the code. Since we now > > > wish to use this mechanism to enumerate features from the floating point > > > feature registers which do not follow this pattern add a width to the > > > table. This means updating all the existing table entries but makes it > > > less likely that we run into issues in future due to implicitly assuming > > > a 4 bit width. > > > > > > Signed-off-by: Mark Brown > > > > Do we leave this one alone on purpose? > > > > .desc = "GIC system register CPU interface", > > .capability = ARM64_HAS_SYSREG_GIC_CPUIF, > > .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, > > .matches = has_useable_gicv3_cpuif, > > .sys_reg = SYS_ID_AA64PFR0_EL1, > > .field_pos = ID_AA64PFR0_GIC_SHIFT, > > .sign = FTR_UNSIGNED, > > .min_field_value = 1, > > > > Since width == 0, it will generate an undefined behavior. > > I don't think that's on purpose, and we should definitely address > this. Maybe we should have a warning if we spot an occurrence of > .width being 0. We should indeed have a check. Alternatively, assume the default to be 4 and convert all 0s to 4 during boot (less patch churn). -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel