From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7F04FC433EF for ; Sat, 19 Feb 2022 07:35:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=lbw9dG5f9umzqzk0M/ND/rjigBO4VJNNhEFnuoc7/Qk=; b=MWSb7jvZTmAunR +8O6C8LT0QHLmi8XYhi8qwb7o6uELEb/ZKwuuKsrUt0ccBoLmrTu0OimK6uTu/ZCbktRmBjHepw/M NfLmDg0GZKQgeDCNkeZnuzEukRSpxB/x2R4KT+LZhDwnTox82mENqSKvPo3qobfSvWU20FkD61jzf MJ0TQStpxUQ8Hqmx+jX7FVfZDZh2ld74wOch+BW91+Hbh7MdNxgU/APJaXIBVyHqupEUPS6VXudOj 7Sv3PuIwsRB0hQno0NMvWE24auw95Qoamj/SrD6hFiO0gpuQ7rdKu2PG9tQFEwZd65KPyQjXMgrYX KQlMKeVPjJ3znjE7vWIg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nLKEu-00GN6b-M6; Sat, 19 Feb 2022 07:33:08 +0000 Received: from perceval.ideasonboard.com ([213.167.242.64]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nLKEq-00GN5i-Dx for linux-arm-kernel@lists.infradead.org; Sat, 19 Feb 2022 07:33:06 +0000 Received: from pendragon.ideasonboard.com (62-78-145-57.bb.dnainternet.fi [62.78.145.57]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 61F7547F; Sat, 19 Feb 2022 08:33:01 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1645255981; bh=1PcP5NFUlV2CZ2sRFjeLtMwSCSCVUNTVqMR/f+jeDUU=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=FWm5NR5iQyCOSoUgQbNs7teuS0y4K/xVG3fiupAkFpGbHyMGpQ7eCNdBR66EvXt+I B9y0NrFp3lIofDqcZK8oiSDFheK3K8lhFH4XZ1j9+eJvFfv1JYSAlf40eKz/jufhjI aPMhYWQz8sO+CmbwaPBhjcnpgzMVdTgXTyizEZUQ= Date: Sat, 19 Feb 2022 09:32:51 +0200 From: Laurent Pinchart To: Lucas Stach Cc: Shawn Guo , Rob Herring , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, patchwork-lst@pengutronix.de Subject: Re: [PATCH v2 1/9] soc: imx: gpcv2: add PGC control register indirection Message-ID: References: <20220207192547.1997549-1-l.stach@pengutronix.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220207192547.1997549-1-l.stach@pengutronix.de> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220218_233304_679757_24A221A8 X-CRM114-Status: GOOD ( 23.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Lucas, Thank you for the patch. On Mon, Feb 07, 2022 at 08:25:39PM +0100, Lucas Stach wrote: > The PGC control registers in the shared (not per-PGC) region of the > GPC address space have different offsets on i.MX8MP to make space for > additional interrupt control registers. > > Signed-off-by: Lucas Stach Reviewed-by: Laurent Pinchart > --- > drivers/soc/imx/gpcv2.c | 43 ++++++++++++++++++++++++++++++----------- > 1 file changed, 32 insertions(+), 11 deletions(-) > > diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c > index 3e59d479d001..01f46b078df3 100644 > --- a/drivers/soc/imx/gpcv2.c > +++ b/drivers/soc/imx/gpcv2.c > @@ -184,9 +184,17 @@ > > #define GPC_PGC_CTRL_PCR BIT(0) > > +struct imx_pgc_regs { > + u16 map; > + u16 pup; > + u16 pdn; > + u16 hsk; > +}; > + > struct imx_pgc_domain { > struct generic_pm_domain genpd; > struct regmap *regmap; > + const struct imx_pgc_regs *regs; > struct regulator *regulator; > struct reset_control *reset; > struct clk_bulk_data *clks; > @@ -210,6 +218,7 @@ struct imx_pgc_domain_data { > const struct imx_pgc_domain *domains; > size_t domains_num; > const struct regmap_access_table *reg_access_table; > + const struct imx_pgc_regs *pgc_regs; > }; > > static inline struct imx_pgc_domain * > @@ -249,14 +258,14 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) > > if (domain->bits.pxx) { > /* request the domain to power up */ > - regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, > + regmap_update_bits(domain->regmap, domain->regs->pup, > domain->bits.pxx, domain->bits.pxx); > /* > * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait > * for PUP_REQ/PDN_REQ bit to be cleared > */ > ret = regmap_read_poll_timeout(domain->regmap, > - GPC_PU_PGC_SW_PUP_REQ, reg_val, > + domain->regs->pup, reg_val, > !(reg_val & domain->bits.pxx), > 0, USEC_PER_MSEC); > if (ret) { > @@ -278,11 +287,11 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) > > /* request the ADB400 to power up */ > if (domain->bits.hskreq) { > - regmap_update_bits(domain->regmap, GPC_PU_PWRHSK, > + regmap_update_bits(domain->regmap, domain->regs->hsk, > domain->bits.hskreq, domain->bits.hskreq); > > /* > - * ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK, reg_val, > + * ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk, reg_val, > * (reg_val & domain->bits.hskack), 0, > * USEC_PER_MSEC); > * Technically we need the commented code to wait handshake. But that needs > @@ -329,10 +338,10 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd) > > /* request the ADB400 to power down */ > if (domain->bits.hskreq) { > - regmap_clear_bits(domain->regmap, GPC_PU_PWRHSK, > + regmap_clear_bits(domain->regmap, domain->regs->hsk, > domain->bits.hskreq); > > - ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK, > + ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk, > reg_val, > !(reg_val & domain->bits.hskack), > 0, USEC_PER_MSEC); > @@ -350,14 +359,14 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd) > } > > /* request the domain to power down */ > - regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ, > + regmap_update_bits(domain->regmap, domain->regs->pdn, > domain->bits.pxx, domain->bits.pxx); > /* > * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait > * for PUP_REQ/PDN_REQ bit to be cleared > */ > ret = regmap_read_poll_timeout(domain->regmap, > - GPC_PU_PGC_SW_PDN_REQ, reg_val, > + domain->regs->pdn, reg_val, > !(reg_val & domain->bits.pxx), > 0, USEC_PER_MSEC); > if (ret) { > @@ -441,10 +450,18 @@ static const struct regmap_access_table imx7_access_table = { > .n_yes_ranges = ARRAY_SIZE(imx7_yes_ranges), > }; > > +static const struct imx_pgc_regs imx7_pgc_regs = { > + .map = GPC_PGC_CPU_MAPPING, > + .pup = GPC_PU_PGC_SW_PUP_REQ, > + .pdn = GPC_PU_PGC_SW_PDN_REQ, > + .hsk = GPC_PU_PWRHSK, > +}; > + > static const struct imx_pgc_domain_data imx7_pgc_domain_data = { > .domains = imx7_pgc_domains, > .domains_num = ARRAY_SIZE(imx7_pgc_domains), > .reg_access_table = &imx7_access_table, > + .pgc_regs = &imx7_pgc_regs, > }; > > static const struct imx_pgc_domain imx8m_pgc_domains[] = { > @@ -613,6 +630,7 @@ static const struct imx_pgc_domain_data imx8m_pgc_domain_data = { > .domains = imx8m_pgc_domains, > .domains_num = ARRAY_SIZE(imx8m_pgc_domains), > .reg_access_table = &imx8m_access_table, > + .pgc_regs = &imx7_pgc_regs, > }; > > static const struct imx_pgc_domain imx8mm_pgc_domains[] = { > @@ -803,6 +821,7 @@ static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = { > .domains = imx8mm_pgc_domains, > .domains_num = ARRAY_SIZE(imx8mm_pgc_domains), > .reg_access_table = &imx8mm_access_table, > + .pgc_regs = &imx7_pgc_regs, > }; > > static const struct imx_pgc_domain imx8mn_pgc_domains[] = { > @@ -894,6 +913,7 @@ static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = { > .domains = imx8mn_pgc_domains, > .domains_num = ARRAY_SIZE(imx8mn_pgc_domains), > .reg_access_table = &imx8mn_access_table, > + .pgc_regs = &imx7_pgc_regs, > }; > > static int imx_pgc_domain_probe(struct platform_device *pdev) > @@ -926,7 +946,7 @@ static int imx_pgc_domain_probe(struct platform_device *pdev) > pm_runtime_enable(domain->dev); > > if (domain->bits.map) > - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, > + regmap_update_bits(domain->regmap, domain->regs->map, > domain->bits.map, domain->bits.map); > > ret = pm_genpd_init(&domain->genpd, NULL, true); > @@ -952,7 +972,7 @@ static int imx_pgc_domain_probe(struct platform_device *pdev) > pm_genpd_remove(&domain->genpd); > out_domain_unmap: > if (domain->bits.map) > - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, > + regmap_update_bits(domain->regmap, domain->regs->map, > domain->bits.map, 0); > pm_runtime_disable(domain->dev); > > @@ -967,7 +987,7 @@ static int imx_pgc_domain_remove(struct platform_device *pdev) > pm_genpd_remove(&domain->genpd); > > if (domain->bits.map) > - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, > + regmap_update_bits(domain->regmap, domain->regs->map, > domain->bits.map, 0); > > pm_runtime_disable(domain->dev); > @@ -1098,6 +1118,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev) > > domain = pd_pdev->dev.platform_data; > domain->regmap = regmap; > + domain->regs = domain_data->pgc_regs; > domain->genpd.power_on = imx_pgc_power_up; > domain->genpd.power_off = imx_pgc_power_down; > > -- Regards, Laurent Pinchart _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel