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Tue, 22 Feb 2022 02:01:44 -0800 (PST) Date: Tue, 22 Feb 2022 11:01:41 +0100 From: Corentin Labbe To: Harsha Cc: herbert@gondor.apana.org.au, davem@davemloft.net, linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, michals@xilinx.com, saratcha@xilinx.com, harshj@xilinx.com, git@xilinx.com Subject: Re: [PATCH V2 3/4] crypto: xilinx: Add Xilinx SHA3 driver Message-ID: References: <1645125264-11033-1-git-send-email-harsha.harsha@xilinx.com> <1645125264-11033-4-git-send-email-harsha.harsha@xilinx.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1645125264-11033-4-git-send-email-harsha.harsha@xilinx.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220222_020146_265822_D4711985 X-CRM114-Status: GOOD ( 30.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Le Fri, Feb 18, 2022 at 12:44:23AM +0530, Harsha a =E9crit : > This patch adds SHA3 driver support for the Xilinx ZynqMP SoC. > Xilinx ZynqMP SoC has SHA3 engine used for secure hash calculation. > The flow is > SHA3 request from Userspace -> SHA3 driver-> ZynqMp driver-> Firmware -> > SHA3 HW Engine > = > SHA3 HW engine in Xilinx ZynqMP SoC, does not support parallel processing > of 2 hash requests. > Therefore, software fallback is being used for init, update, final, > export and import in the ZynqMP SHA driver > For digest, the calculation of SHA3 hash is done by the hardened > SHA3 accelerator in Xilinx ZynqMP SoC. > = > Signed-off-by: Harsha > --- > drivers/crypto/Kconfig | 10 ++ > drivers/crypto/xilinx/Makefile | 1 + > drivers/crypto/xilinx/zynqmp-sha.c | 285 +++++++++++++++++++++++++++++++= ++++++ > 3 files changed, 296 insertions(+) > create mode 100644 drivers/crypto/xilinx/zynqmp-sha.c > = > diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig > index 4f70567..bf4e55e 100644 > --- a/drivers/crypto/Kconfig > +++ b/drivers/crypto/Kconfig > @@ -808,6 +808,16 @@ config CRYPTO_DEV_ZYNQMP_AES > accelerator. Select this if you want to use the ZynqMP module > for AES algorithms. > = > +config CRYPTO_DEV_ZYNQMP_SHA3 > + bool "Support for Xilinx ZynqMP SHA3 hardware accelerator" > + depends on ARCH_ZYNQMP > + select CRYPTO_SHA3 > + help > + Xilinx ZynqMP has SHA3 engine used for secure hash calculation. > + This driver interfaces with SHA3 hardware engine. > + Select this if you want to use the ZynqMP module > + for SHA3 hash computation. > + > source "drivers/crypto/chelsio/Kconfig" > = > source "drivers/crypto/virtio/Kconfig" > diff --git a/drivers/crypto/xilinx/Makefile b/drivers/crypto/xilinx/Makef= ile > index 534e32d..730feff 100644 > --- a/drivers/crypto/xilinx/Makefile > +++ b/drivers/crypto/xilinx/Makefile > @@ -1,2 +1,3 @@ > # SPDX-License-Identifier: GPL-2.0-only > obj-$(CONFIG_CRYPTO_DEV_ZYNQMP_AES) +=3D zynqmp-aes-gcm.o > +obj-$(CONFIG_CRYPTO_DEV_ZYNQMP_SHA3) +=3D zynqmp-sha.o > diff --git a/drivers/crypto/xilinx/zynqmp-sha.c b/drivers/crypto/xilinx/z= ynqmp-sha.c > new file mode 100644 > index 0000000..1eaca97 > --- /dev/null > +++ b/drivers/crypto/xilinx/zynqmp-sha.c > @@ -0,0 +1,285 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Xilinx ZynqMP SHA Driver. > + * Copyright (c) 2022 Xilinx Inc. > + */ > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define ZYNQMP_DMA_BIT_MASK 32U > +#define ZYNQMP_DMA_ALLOC_FIXED_SIZE 0x1000U > + > +enum zynqmp_sha_op { > + ZYNQMP_SHA3_INIT =3D 1, > + ZYNQMP_SHA3_UPDATE =3D 2, > + ZYNQMP_SHA3_FINAL =3D 4, > +}; > + > +struct zynqmp_sha_drv_ctx { > + struct shash_alg sha3_384; > + struct device *dev; > +}; > + > +struct zynqmp_sha_tfm_ctx { > + struct device *dev; > + struct crypto_shash *fbk_tfm; > +}; > + > +struct zynqmp_sha_desc_ctx { > + struct shash_desc fbk_req; > +}; > + > +static dma_addr_t update_dma_addr, final_dma_addr; > +static char *ubuf, *fbuf; > + > +static int zynqmp_sha_init_tfm(struct crypto_shash *hash) > +{ > + const char *fallback_driver_name =3D crypto_shash_alg_name(hash); > + struct zynqmp_sha_tfm_ctx *tfm_ctx =3D crypto_shash_ctx(hash); > + struct shash_alg *alg =3D crypto_shash_alg(hash); > + struct crypto_shash *fallback_tfm; > + struct zynqmp_sha_drv_ctx *drv_ctx; > + > + drv_ctx =3D container_of(alg, struct zynqmp_sha_drv_ctx, sha3_384); > + tfm_ctx->dev =3D drv_ctx->dev; > + > + /* Allocate a fallback and abort if it failed. */ > + fallback_tfm =3D crypto_alloc_shash(fallback_driver_name, 0, > + CRYPTO_ALG_NEED_FALLBACK); > + if (IS_ERR(fallback_tfm)) > + return PTR_ERR(fallback_tfm); > + > + tfm_ctx->fbk_tfm =3D fallback_tfm; > + hash->descsize +=3D crypto_shash_descsize(tfm_ctx->fbk_tfm); > + > + return 0; > +} > + > +static void zynqmp_sha_exit_tfm(struct crypto_shash *hash) > +{ > + struct zynqmp_sha_tfm_ctx *tfm_ctx =3D crypto_shash_ctx(hash); > + > + if (tfm_ctx->fbk_tfm) { > + crypto_free_shash(tfm_ctx->fbk_tfm); > + tfm_ctx->fbk_tfm =3D NULL; > + } > + > + memzero_explicit(tfm_ctx, sizeof(struct zynqmp_sha_tfm_ctx)); > +} > + > +static int zynqmp_sha_init(struct shash_desc *desc) > +{ > + struct zynqmp_sha_desc_ctx *dctx =3D shash_desc_ctx(desc); > + struct zynqmp_sha_tfm_ctx *tctx =3D crypto_shash_ctx(desc->tfm); > + > + dctx->fbk_req.tfm =3D tctx->fbk_tfm; > + return crypto_shash_init(&dctx->fbk_req); > +} > + > +static int zynqmp_sha_update(struct shash_desc *desc, const u8 *data, un= signed int length) > +{ > + struct zynqmp_sha_desc_ctx *dctx =3D shash_desc_ctx(desc); > + > + return crypto_shash_update(&dctx->fbk_req, data, length); > +} > + > +static int zynqmp_sha_final(struct shash_desc *desc, u8 *out) > +{ > + struct zynqmp_sha_desc_ctx *dctx =3D shash_desc_ctx(desc); > + > + return crypto_shash_final(&dctx->fbk_req, out); > +} > + > +static int zynqmp_sha_finup(struct shash_desc *desc, const u8 *data, uns= igned int length, u8 *out) > +{ > + struct zynqmp_sha_desc_ctx *dctx =3D shash_desc_ctx(desc); > + > + return crypto_shash_finup(&dctx->fbk_req, data, length, out); > +} > + > +static int zynqmp_sha_import(struct shash_desc *desc, const void *in) > +{ > + struct zynqmp_sha_desc_ctx *dctx =3D shash_desc_ctx(desc); > + struct zynqmp_sha_tfm_ctx *tctx =3D crypto_shash_ctx(desc->tfm); > + > + dctx->fbk_req.tfm =3D tctx->fbk_tfm; > + return crypto_shash_import(&dctx->fbk_req, in); > +} > + > +static int zynqmp_sha_export(struct shash_desc *desc, void *out) > +{ > + struct zynqmp_sha_desc_ctx *dctx =3D shash_desc_ctx(desc); > + > + return crypto_shash_export(&dctx->fbk_req, out); > +} > + > +static int zynqmp_sha_digest(struct shash_desc *desc, const u8 *data, un= signed int len, u8 *out) > +{ > + unsigned int remaining_len =3D len; > + int update_size; > + int ret; > + > + ret =3D zynqmp_pm_sha_hash(0, 0, ZYNQMP_SHA3_INIT); > + if (ret) > + return ret; > + > + while (remaining_len !=3D 0) { > + memset(ubuf, 0, ZYNQMP_DMA_ALLOC_FIXED_SIZE); > + if (remaining_len >=3D ZYNQMP_DMA_ALLOC_FIXED_SIZE) { > + update_size =3D ZYNQMP_DMA_ALLOC_FIXED_SIZE; > + remaining_len -=3D ZYNQMP_DMA_ALLOC_FIXED_SIZE; > + } else { > + update_size =3D remaining_len; > + remaining_len =3D 0; > + } > + memcpy(ubuf, data, update_size); > + flush_icache_range((unsigned long)ubuf, (unsigned long)ubuf + update_s= ize); Hello Why do you copy all data before processing and not use them in-place ? > + ret =3D zynqmp_pm_sha_hash(update_dma_addr, update_size, ZYNQMP_SHA3_U= PDATE); > + if (ret) > + return ret; > + > + data +=3D update_size; > + } > + > + ret =3D zynqmp_pm_sha_hash(final_dma_addr, SHA3_384_DIGEST_SIZE, ZYNQMP= _SHA3_FINAL); > + memcpy(out, fbuf, SHA3_384_DIGEST_SIZE); > + memset(fbuf, 0, SHA3_384_DIGEST_SIZE); You should use memzero_explicit() Regards _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel