Re: [RFC PATCH 4/6] drm: mxc-epdc: Add update management

From: "Jonathan Neuschäfer" <j.neuschaefer@gmx.net>
To: Andreas Kemnade <andreas@kemnade.info>
Cc: p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch,
	robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
	kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
	maarten.lankhorst@linux.intel.com, mripard@kernel.org,
	tzimmermann@suse.de, dri-devel@lists.freedesktop.org,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, alistair@alistair23.me,
	samuel@sholland.org, josua.mayer@jm0.eu,
	letux-kernel@openphoenux.org
Subject: Re: [RFC PATCH 4/6] drm: mxc-epdc: Add update management
Date: Sat, 12 Mar 2022 21:21:58 +0100	[thread overview]
Message-ID: <Yi0A5inJh0Whkh5n@latitude> (raw)
In-Reply-To: <20220206080016.796556-5-andreas@kemnade.info>

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On Sun, Feb 06, 2022 at 09:00:14AM +0100, Andreas Kemnade wrote:
> The EPDC can process some dirty rectangles at a time, pick them up and
> forward them to the controller. Only processes not involving PXP are
> supported at the moment. Due to that and to work with more waveforms,
> there is some masking/shifting done. It was tested with the factory
> waveforms of Kobo Clara HD, Tolino Shine 3, and Tolino Shine 2HD.
> Also the waveform called epdc_E060SCM.fw from NXP BSP works with the
> i.MX6SL devices.
> 
> Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
> ---

[...]
> +	adj_update_region = upd_data_list->update_desc->upd_data.update_region;
> +	/*
> +	 * Is the working buffer idle?
> +	 * If the working buffer is busy, we must wait for the resource
> +	 * to become free. The IST will signal this event.

What does IST mean?

> +void mxc_epdc_draw_mode0(struct mxc_epdc *priv)

What does mode 0 imply? An overview of the possible modes would be
appreciated.

> +{
> +	u32 *upd_buf_ptr;
> +	int i;
> +	u32 xres, yres;
> +
> +	upd_buf_ptr = (u32 *)priv->epdc_mem_virt;
> +
> +	epdc_working_buf_intr(priv, true);
> +	epdc_lut_complete_intr(priv, 0, true);
> +
> +	/* Use unrotated (native) width/height */
> +	xres = priv->epdc_mem_width;
> +	yres = priv->epdc_mem_height;
> +
> +	/* Program EPDC update to process buffer */
> +	epdc_set_update_area(priv, priv->epdc_mem_phys, 0, 0, xres, yres, 0);
> +	epdc_submit_update(priv, 0, priv->wv_modes.mode_init, UPDATE_MODE_FULL,
> +		false, true, 0xFF);
> +
> +	dev_dbg(priv->drm.dev, "Mode0 update - Waiting for LUT to complete...\n");
> +
> +	/* Will timeout after ~4-5 seconds */
> +
> +	for (i = 0; i < 40; i++) {
> +		if (!epdc_is_lut_active(priv, 0)) {
> +			dev_dbg(priv->drm.dev, "Mode0 init complete\n");
> +			return;
> +		}
> +		msleep(100);
> +	}
> +
> +	dev_err(priv->drm.dev, "Mode0 init failed!\n");
> +}

> +#define WAVEFORM_MODE_GLR16			4
> +#define WAVEFORM_MODE_GLD16			5
> +#define WAVEFORM_MODE_AUTO			257

(How) are these mode numbers related to "mode 0"?

Jonathan

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