From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C77C3C433EF for ; Mon, 7 Mar 2022 16:01:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2nYrV9dAh3s5EwlytsIylUx+3f7Wyse+fii/8hXVoVY=; b=Ntd8Lq/A4tKYvX roX30VuLXog2uGTm5Keo/4F0dxme3QSJThQy14r51HQdhFzWShMD4sxqxEj5vXLvyOJiq1DGlbPNi oDe1Y+xlj+fplePrzq7xHKM44Ekqh02Em1TlSwXaUkfcU9mZ1cSOb2nctn4fWpkTy9Lu+Bm3useed ptJ2DTOebzcM6p9kORoHrDnrJ93HyyGRLitQOVuw55RqiIBnBCXC5p044tSen6VG3vbDdhST/j2qG C+T70Idcwo3j94SJtIoj5VDtoys/iASer6hbtG+jDICw3B+5kTnCX2ofZlEcY49P/j+4Xm//KzFSw E90vZ2DlswyxeXeg+BuA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRFmZ-000m7d-Be; Mon, 07 Mar 2022 16:00:23 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nRFmV-000m6c-Q9 for linux-arm-kernel@lists.infradead.org; Mon, 07 Mar 2022 16:00:21 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 735A4B81627; Mon, 7 Mar 2022 16:00:18 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B1973C340EF; Mon, 7 Mar 2022 16:00:15 +0000 (UTC) Date: Mon, 7 Mar 2022 16:00:12 +0000 From: Catalin Marinas To: Marc Zyngier Cc: will@kernel.org, Linu Cherian , tglx@linutronix.de, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuc.decode@gmail.com Subject: Re: [PATCH V3] irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR Message-ID: References: <20220307143014.22758-1-lcherian@marvell.com> <877d9525eq.wl-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <877d9525eq.wl-maz@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220307_080020_018371_AAD83DBD X-CRM114-Status: GOOD ( 25.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Mar 07, 2022 at 02:39:25PM +0000, Marc Zyngier wrote: > On Mon, 07 Mar 2022 14:30:14 +0000, > Linu Cherian wrote: > > > > When a IAR register read races with a GIC interrupt RELEASE event, > > GIC-CPU interface could wrongly return a valid INTID to the CPU > > for an interrupt that is already released(non activated) instead of 0x3ff. > > > > As a side effect, an interrupt handler could run twice, once with > > interrupt priority and then with idle priority. > > > > As a workaround, gic_read_iar is updated so that it will return a > > valid interrupt ID only if there is a change in the active priority list > > after the IAR read on all the affected Silicons. > > > > Since there are silicon variants where both 23154 and 38545 are applicable, > > workaround for erratum 23154 has been extended to address both of them. > > > > Signed-off-by: Linu Cherian > > --- > > Changes since V2: > > - Changed masked part number to individual part numbers > > - Added additional comment to clarify on priority groups > > > > > > Changes since V1: > > - IIDR based quirk management done for 23154 has been reverted > > - Extended existing 23154 errata to address 38545 as well, > > so that existing static keys are reused. > > - Added MIDR based support macros to cover all the affected parts > > - Changed the unlikely construct to likely construct in the workaround > > function. > > > > > > > > > > Documentation/arm64/silicon-errata.rst | 2 +- > > arch/arm64/Kconfig | 8 ++++++-- > > arch/arm64/include/asm/arch_gicv3.h | 23 +++++++++++++++++++++-- > > arch/arm64/include/asm/cputype.h | 13 +++++++++++++ > > arch/arm64/kernel/cpu_errata.c | 20 +++++++++++++++++--- > > 5 files changed, 58 insertions(+), 8 deletions(-) > > Looks good to me this time. > > Catalin, Will: happy to take this into the irqchip tree for 5.18 with > your Ack, or you can take it into the arm64 tree with my > > Reviewed-by: Marc Zyngier Fine by me to take it into irqchip but do a quick check for conflicts with other arm64 changes in for-next/core. Acked-by: Catalin Marinas _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel