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09 Mar 2022 09:40:38 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Wed, 9 Mar 2022 09:40:36 -0800 Received: from qian (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Wed, 9 Mar 2022 09:40:35 -0800 Date: Wed, 9 Mar 2022 12:40:33 -0500 From: Qian Cai To: Linu Cherian CC: , , , , , , Subject: Re: [PATCH V3] irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR Message-ID: References: <20220307143014.22758-1-lcherian@marvell.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220307143014.22758-1-lcherian@marvell.com> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220309_094050_589853_09A29E45 X-CRM114-Status: GOOD ( 13.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Mar 07, 2022 at 08:00:14PM +0530, Linu Cherian wrote: > When a IAR register read races with a GIC interrupt RELEASE event, > GIC-CPU interface could wrongly return a valid INTID to the CPU > for an interrupt that is already released(non activated) instead of 0x3ff. > > As a side effect, an interrupt handler could run twice, once with > interrupt priority and then with idle priority. > > As a workaround, gic_read_iar is updated so that it will return a > valid interrupt ID only if there is a change in the active priority list > after the IAR read on all the affected Silicons. > > Since there are silicon variants where both 23154 and 38545 are applicable, > workaround for erratum 23154 has been extended to address both of them. > > Signed-off-by: Linu Cherian Reverting this commit from today's linux-next fixed global-out-of-bounds accesses running CPU hotplug workloads on a non-ThunderX server. psci: CPU88 killed (polled 0 ms) ================================================================== BUG: KASAN: global-out-of-bounds in is_affected_midr_range_list Read of size 4 at addr ffffa0ec80ddcc6c by task swapper/88/0 CPU: 88 PID: 0 Comm: swapper/88 Not tainted 5.17.0-rc7-next-20220309-dirty #25 Call trace: dump_backtrace show_stack dump_stack_lvl print_address_description.constprop.0 print_report kasan_report __asan_report_load4_noabort is_affected_midr_range_list is_midr_in_range_list at ./arch/arm64/include/asm/cputype.h:221 (inlined by) is_affected_midr_range_list at arch/arm64/kernel/cpu_errata.c:41 verify_local_cpu_caps verify_local_cpu_caps at arch/arm64/kernel/cpufeature.c:2787 check_local_cpu_capabilities verify_local_elf_hwcaps at arch/arm64/kernel/cpufeature.c:2852 (inlined by) verify_local_cpu_capabilities at arch/arm64/kernel/cpufeature.c:2922 (inlined by) check_local_cpu_capabilities at arch/arm64/kernel/cpufeature.c:2948 secondary_start_kernel __secondary_switched The buggy address belongs to the variable: cavium_erratum_23154_cpus The buggy address belongs to the virtual mapping at [ffffa0ec80dd0000, ffffa0ec82140000) created by: map_kernel _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel