* [PATCH 0/4] imx8mp: Add media block control
@ 2022-02-28 15:47 Paul Elder
2022-02-28 15:47 ` [PATCH 1/4] dt-bindings: soc: Add i.MX8MP media block control DT bindings Paul Elder
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Paul Elder @ 2022-02-28 15:47 UTC (permalink / raw)
To: Rob Herring, Shawn Guo, Sascha Hauer
Cc: Paul Elder, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Joakim Zhang, Laurent Pinchart, Peng Fan,
Lucas Stach, Marek Vasut, Daniel Baluta, Zhen Lei, Jacky Bai,
Adam Ford, Frieder Schrempf, Dan Carpenter, devicetree,
linux-arm-kernel
This patch series depends on v2 of the series "soc: imx: gpcv2: add PGC
control register indirection" from Lucas Stach [1].
The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level
peripheral providing access to the NoC and ensuring proper power
sequencing of the peripherals within the MEDIAMIX domain. This patch
series adds DT bindings for it, and expands the imx8m-blk-ctrl driver to
support the i.MX8MP's Media Block Control.
The patches have been tested with with ISI on the i.MX8MP. The ISI
driver is still under development [2], and will be posted in the not too
distant future.
[1] https://lore.kernel.org/all/20220207192547.1997549-1-l.stach@pengutronix.de/
[2] https://gitlab.com/ideasonboard/nxp/linux/-/tree/pinchartl/v5.17/isi
Laurent Pinchart (1):
arm64: dts: imx8mp: Add MEDIAMIX power domains
Paul Elder (3):
dt-bindings: soc: Add i.MX8MP media block control DT bindings
soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
arm64: dts: imx8mp: Add MEDIA_BLK_CTRL
.../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml | 105 +++++++++++++++
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 66 ++++++++++
drivers/soc/imx/imx8m-blk-ctrl.c | 123 +++++++++++++++++-
include/dt-bindings/power/imx8mp-power.h | 10 ++
4 files changed, 302 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
--
2.30.2
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^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 1/4] dt-bindings: soc: Add i.MX8MP media block control DT bindings 2022-02-28 15:47 [PATCH 0/4] imx8mp: Add media block control Paul Elder @ 2022-02-28 15:47 ` Paul Elder 2022-02-28 16:41 ` Laurent Pinchart 2022-03-10 19:53 ` Rob Herring 2022-02-28 15:47 ` [PATCH 2/4] soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl Paul Elder ` (2 subsequent siblings) 3 siblings, 2 replies; 8+ messages in thread From: Paul Elder @ 2022-02-28 15:47 UTC (permalink / raw) To: Rob Herring, Shawn Guo, Sascha Hauer Cc: Paul Elder, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Laurent Pinchart, Lucas Stach, devicetree, linux-arm-kernel The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral providing access to the NoC and ensuring proper power sequencing of the peripherals within the MEDIAMIX domain. Add DT bindings for it. There is already a driver for block controls of other SoCs in the i.MX8M family, so these bindings will expand upon that. Signed-off-by: Paul Elder <paul.elder@ideasonboard.com> --- .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml | 105 ++++++++++++++++++ include/dt-bindings/power/imx8mp-power.h | 10 ++ 2 files changed, 115 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml new file mode 100644 index 000000000000..b41a8802081a --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MP Media Block Control + +maintainers: + - Paul Elder <paul.elder@ideasonboard.com> + +description: + The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral + providing access to the NoC and ensuring proper power sequencing of the + peripherals within the MEDIAMIX domain. + +properties: + compatible: + items: + - const: fsl,imx8mp-media-blk-ctrl + - const: syscon + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + maxItems: 10 + + power-domain-names: + items: + - const: bus + - const: mipi-dsi1 + - const: mipi-csi1 + - const: lcdif1 + - const: isi + - const: mipi-csi2 + - const: lcdif2 + - const: isp + - const: dwe + - const: mipi-dsi2 + + clocks: + items: + - description: The APB clock + - description: The AXI clock + - description: The pixel clock for the first CSI2 receiver (aclk) + - description: The pixel clock for the second CSI2 receiver (aclk) + - description: The pixel clock for the first LCDIF (pix_clk) + - description: The pixel clock for the second LCDIF (pix_clk) + - description: The core clock for the ISP (clk) + - description: The MIPI-PHY reference clock used by DSI + + clock-names: + items: + - const: apb + - const: axi + - const: cam1 + - const: cam2 + - const: disp1 + - const: disp2 + - const: isp + - const: phy + +required: + - compatible + - reg + - '#power-domain-cells' + - power-domains + - power-domain-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8mp-clock.h> + #include <dt-bindings/power/imx8mp-power.h> + + media_blk_ctl: blk-ctl@32ec0000 { + compatible = "fsl,imx8mp-media-blk-ctrl", "syscon"; + reg = <0x32ec0000 0x10000>; + power-domains = <&mediamix_pd>, <&mipi_phy1_pd>, + <&mipi_phy1_pd>, <&mediamix_pd>, + <&mediamix_pd>, <&mipi_phy2_pd>, + <&mediamix_pd>, <&ispdwp_pd>, + <&ispdwp_pd>, <&mipi_phy2_pd>; + power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", "lcdif1", "isi", + "mipi-csi2", "lcdif2", "isp", "dwe", "mipi-dsi2"; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>; + clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2", + "isp", "phy"; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h index 9f90c40a2c6c..bc8458f1e725 100644 --- a/include/dt-bindings/power/imx8mp-power.h +++ b/include/dt-bindings/power/imx8mp-power.h @@ -32,4 +32,14 @@ #define IMX8MP_HSIOBLK_PD_PCIE 3 #define IMX8MP_HSIOBLK_PD_PCIE_PHY 4 +#define IMX8MP_MEDIABLK_PD_MIPI_DSI_1 0 +#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_1 1 +#define IMX8MP_MEDIABLK_PD_LCDIF_1 2 +#define IMX8MP_MEDIABLK_PD_ISI 3 +#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_2 4 +#define IMX8MP_MEDIABLK_PD_LCDIF_2 5 +#define IMX8MP_MEDIABLK_PD_ISP 6 +#define IMX8MP_MEDIABLK_PD_DWE 7 +#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 8 + #endif -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/4] dt-bindings: soc: Add i.MX8MP media block control DT bindings 2022-02-28 15:47 ` [PATCH 1/4] dt-bindings: soc: Add i.MX8MP media block control DT bindings Paul Elder @ 2022-02-28 16:41 ` Laurent Pinchart 2022-03-10 19:53 ` Rob Herring 1 sibling, 0 replies; 8+ messages in thread From: Laurent Pinchart @ 2022-02-28 16:41 UTC (permalink / raw) To: Paul Elder Cc: Rob Herring, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Lucas Stach, devicetree, linux-arm-kernel Hi Paul, Thank you for the patch. On Tue, Mar 01, 2022 at 12:47:58AM +0900, Paul Elder wrote: > The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level > peripheral providing access to the NoC and ensuring proper power > sequencing of the peripherals within the MEDIAMIX domain. Add DT > bindings for it. > > There is already a driver for block controls of other SoCs in the i.MX8M > family, so these bindings will expand upon that. > > Signed-off-by: Paul Elder <paul.elder@ideasonboard.com> > --- > .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml | 105 ++++++++++++++++++ > include/dt-bindings/power/imx8mp-power.h | 10 ++ > 2 files changed, 115 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml > > diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml > new file mode 100644 > index 000000000000..b41a8802081a > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml > @@ -0,0 +1,105 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP i.MX8MP Media Block Control > + > +maintainers: > + - Paul Elder <paul.elder@ideasonboard.com> > + > +description: > + The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral > + providing access to the NoC and ensuring proper power sequencing of the > + peripherals within the MEDIAMIX domain. > + > +properties: > + compatible: > + items: > + - const: fsl,imx8mp-media-blk-ctrl > + - const: syscon > + > + reg: > + maxItems: 1 > + > + '#power-domain-cells': > + const: 1 > + > + power-domains: > + maxItems: 10 > + > + power-domain-names: > + items: > + - const: bus > + - const: mipi-dsi1 > + - const: mipi-csi1 > + - const: lcdif1 > + - const: isi > + - const: mipi-csi2 > + - const: lcdif2 > + - const: isp > + - const: dwe > + - const: mipi-dsi2 > + > + clocks: > + items: > + - description: The APB clock > + - description: The AXI clock > + - description: The pixel clock for the first CSI2 receiver (aclk) > + - description: The pixel clock for the second CSI2 receiver (aclk) > + - description: The pixel clock for the first LCDIF (pix_clk) > + - description: The pixel clock for the second LCDIF (pix_clk) > + - description: The core clock for the ISP (clk) > + - description: The MIPI-PHY reference clock used by DSI > + > + clock-names: > + items: > + - const: apb > + - const: axi > + - const: cam1 > + - const: cam2 > + - const: disp1 > + - const: disp2 > + - const: isp > + - const: phy > + > +required: > + - compatible > + - reg > + - '#power-domain-cells' > + - power-domains > + - power-domain-names > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/imx8mp-clock.h> > + #include <dt-bindings/power/imx8mp-power.h> > + > + media_blk_ctl: blk-ctl@32ec0000 { > + compatible = "fsl,imx8mp-media-blk-ctrl", "syscon"; > + reg = <0x32ec0000 0x10000>; 0x138 should be enough for the size. With this fixed, Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > + power-domains = <&mediamix_pd>, <&mipi_phy1_pd>, > + <&mipi_phy1_pd>, <&mediamix_pd>, > + <&mediamix_pd>, <&mipi_phy2_pd>, > + <&mediamix_pd>, <&ispdwp_pd>, > + <&ispdwp_pd>, <&mipi_phy2_pd>; > + power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", "lcdif1", "isi", > + "mipi-csi2", "lcdif2", "isp", "dwe", "mipi-dsi2"; > + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, > + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, > + <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, > + <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, > + <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, > + <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, > + <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, > + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>; > + clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2", > + "isp", "phy"; > + #power-domain-cells = <1>; > + }; > +... > diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h > index 9f90c40a2c6c..bc8458f1e725 100644 > --- a/include/dt-bindings/power/imx8mp-power.h > +++ b/include/dt-bindings/power/imx8mp-power.h > @@ -32,4 +32,14 @@ > #define IMX8MP_HSIOBLK_PD_PCIE 3 > #define IMX8MP_HSIOBLK_PD_PCIE_PHY 4 > > +#define IMX8MP_MEDIABLK_PD_MIPI_DSI_1 0 > +#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_1 1 > +#define IMX8MP_MEDIABLK_PD_LCDIF_1 2 > +#define IMX8MP_MEDIABLK_PD_ISI 3 > +#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_2 4 > +#define IMX8MP_MEDIABLK_PD_LCDIF_2 5 > +#define IMX8MP_MEDIABLK_PD_ISP 6 > +#define IMX8MP_MEDIABLK_PD_DWE 7 > +#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 8 > + > #endif -- Regards, Laurent Pinchart _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/4] dt-bindings: soc: Add i.MX8MP media block control DT bindings 2022-02-28 15:47 ` [PATCH 1/4] dt-bindings: soc: Add i.MX8MP media block control DT bindings Paul Elder 2022-02-28 16:41 ` Laurent Pinchart @ 2022-03-10 19:53 ` Rob Herring 1 sibling, 0 replies; 8+ messages in thread From: Rob Herring @ 2022-03-10 19:53 UTC (permalink / raw) To: Paul Elder Cc: Rob Herring, Laurent Pinchart, devicetree, linux-arm-kernel, Pengutronix Kernel Team, Sascha Hauer, NXP Linux Team, Fabio Estevam, Shawn Guo, Lucas Stach On Tue, 01 Mar 2022 00:47:58 +0900, Paul Elder wrote: > The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level > peripheral providing access to the NoC and ensuring proper power > sequencing of the peripherals within the MEDIAMIX domain. Add DT > bindings for it. > > There is already a driver for block controls of other SoCs in the i.MX8M > family, so these bindings will expand upon that. > > Signed-off-by: Paul Elder <paul.elder@ideasonboard.com> > --- > .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml | 105 ++++++++++++++++++ > include/dt-bindings/power/imx8mp-power.h | 10 ++ > 2 files changed, 115 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml > Reviewed-by: Rob Herring <robh@kernel.org> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/4] soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl 2022-02-28 15:47 [PATCH 0/4] imx8mp: Add media block control Paul Elder 2022-02-28 15:47 ` [PATCH 1/4] dt-bindings: soc: Add i.MX8MP media block control DT bindings Paul Elder @ 2022-02-28 15:47 ` Paul Elder 2022-02-28 16:45 ` Laurent Pinchart 2022-02-28 15:48 ` [PATCH 3/4] arm64: dts: imx8mp: Add MEDIAMIX power domains Paul Elder 2022-02-28 15:48 ` [PATCH 4/4] arm64: dts: imx8mp: Add MEDIA_BLK_CTRL Paul Elder 3 siblings, 1 reply; 8+ messages in thread From: Paul Elder @ 2022-02-28 15:47 UTC (permalink / raw) To: Shawn Guo, Sascha Hauer Cc: Paul Elder, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Laurent Pinchart, Lucas Stach, Adam Ford, Dan Carpenter, Philipp Zabel, linux-arm-kernel Add the description for the i.MX8MP media blk-ctrl. Signed-off-by: Paul Elder <paul.elder@ideasonboard.com> --- drivers/soc/imx/imx8m-blk-ctrl.c | 123 ++++++++++++++++++++++++++++++- 1 file changed, 121 insertions(+), 2 deletions(-) diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c index 511e74f0db8a..a0a0d2d7ca4a 100644 --- a/drivers/soc/imx/imx8m-blk-ctrl.c +++ b/drivers/soc/imx/imx8m-blk-ctrl.c @@ -15,10 +15,11 @@ #include <dt-bindings/power/imx8mm-power.h> #include <dt-bindings/power/imx8mn-power.h> +#include <dt-bindings/power/imx8mp-power.h> #define BLK_SFT_RSTN 0x0 #define BLK_CLK_EN 0x4 -#define BLK_MIPI_RESET_DIV 0x8 /* Mini/Nano DISPLAY_BLK_CTRL only */ +#define BLK_MIPI_RESET_DIV 0x8 /* Mini/Nano/Plus DISPLAY_BLK_CTRL only */ struct imx8m_blk_ctrl_domain; @@ -40,7 +41,7 @@ struct imx8m_blk_ctrl_domain_data { u32 clk_mask; /* - * i.MX8M Mini and Nano have a third DISPLAY_BLK_CTRL register + * i.MX8M Mini, Nano and Plus have a third DISPLAY_BLK_CTRL register * which is used to control the reset for the MIPI Phy. * Since it's only present in certain circumstances, * an if-statement should be used before setting and clearing this @@ -589,6 +590,121 @@ static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = { .num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data), }; +static int imx8mp_media_power_notifier(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, + power_nb); + + if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) + return NOTIFY_OK; + + /* Enable bus clock and deassert bus reset */ + regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8)); + regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8)); + + /* + * On power up we have no software backchannel to the GPC to + * wait for the ADB handshake to happen, so we just delay for a + * bit. On power down the GPC driver waits for the handshake. + */ + if (action == GENPD_NOTIFY_ON) + udelay(5); + + return NOTIFY_OK; +} + +/* + * From i.MX 8M Plus Applications Processor Reference Manual, Rev. 1, + * section 13.2.2, 13.2.3 + * isp-ahb and dwe are not in Figure 13-5. Media BLK_CTRL Clocks + */ +static const struct imx8m_blk_ctrl_domain_data imx8mp_media_blk_ctl_domain_data[] = { + [IMX8MP_MEDIABLK_PD_MIPI_DSI_1] = { + .name = "mediablk-mipi-dsi-1", + .clk_names = (const char *[]){ "apb", "phy", }, + .num_clks = 2, + .gpc_name = "mipi-dsi1", + .rst_mask = BIT(0) | BIT(1), + .clk_mask = BIT(0) | BIT(1), + .mipi_phy_rst_mask = BIT(17), + }, + [IMX8MP_MEDIABLK_PD_MIPI_CSI2_1] = { + .name = "mediablk-mipi-csi2-1", + .clk_names = (const char *[]){ "apb", "cam1" }, + .num_clks = 2, + .gpc_name = "mipi-csi1", + .rst_mask = BIT(2) | BIT(3), + .clk_mask = BIT(2) | BIT(3), + .mipi_phy_rst_mask = BIT(16), + }, + [IMX8MP_MEDIABLK_PD_LCDIF_1] = { + .name = "mediablk-lcdif-1", + .clk_names = (const char *[]){ "disp1", "apb", "axi", }, + .num_clks = 3, + .gpc_name = "lcdif1", + .rst_mask = BIT(4) | BIT(5) | BIT(23), + .clk_mask = BIT(4) | BIT(5) | BIT(23), + }, + [IMX8MP_MEDIABLK_PD_ISI] = { + .name = "mediablk-isi", + .clk_names = (const char *[]){ "axi", "apb" }, + .num_clks = 2, + .gpc_name = "isi", + .rst_mask = BIT(6) | BIT(7), + .clk_mask = BIT(6) | BIT(7), + }, + [IMX8MP_MEDIABLK_PD_MIPI_CSI2_2] = { + .name = "mediablk-mipi-csi2-2", + .clk_names = (const char *[]){ "apb", "cam2" }, + .num_clks = 2, + .gpc_name = "mipi-csi2", + .rst_mask = BIT(9) | BIT(10), + .clk_mask = BIT(9) | BIT(10), + .mipi_phy_rst_mask = BIT(30), + }, + [IMX8MP_MEDIABLK_PD_LCDIF_2] = { + .name = "mediablk-lcdif-2", + .clk_names = (const char *[]){ "disp1", "apb", "axi", }, + .num_clks = 3, + .gpc_name = "lcdif2", + .rst_mask = BIT(11) | BIT(12) | BIT(24), + .clk_mask = BIT(11) | BIT(12) | BIT(24), + }, + [IMX8MP_MEDIABLK_PD_ISP] = { + .name = "mediablk-isp", + .clk_names = (const char *[]){ "isp", "axi", "apb" }, + .num_clks = 3, + .gpc_name = "isp", + .rst_mask = BIT(16) | BIT(17) | BIT(18), + .clk_mask = BIT(16) | BIT(17) | BIT(18), + }, + [IMX8MP_MEDIABLK_PD_DWE] = { + .name = "mediablk-dwe", + .clk_names = (const char *[]){ "axi", "apb" }, + .num_clks = 2, + .gpc_name = "dwe", + .rst_mask = BIT(19) | BIT(20) | BIT(21), + .clk_mask = BIT(19) | BIT(20) | BIT(21), + }, + [IMX8MP_MEDIABLK_PD_MIPI_DSI_2] = { + .name = "mediablk-mipi-dsi-2", + .clk_names = (const char *[]){ "phy", }, + .num_clks = 1, + .gpc_name = "mipi-dsi2", + .rst_mask = BIT(22), + .clk_mask = BIT(22), + .mipi_phy_rst_mask = BIT(29), + }, +}; + +static const struct imx8m_blk_ctrl_data imx8mp_media_blk_ctl_dev_data = { + .max_reg = 0x138, + .power_notifier_fn = imx8mp_media_power_notifier, + .domains = imx8mp_media_blk_ctl_domain_data, + .num_domains = ARRAY_SIZE(imx8mp_media_blk_ctl_domain_data), +}; + static const struct of_device_id imx8m_blk_ctrl_of_match[] = { { .compatible = "fsl,imx8mm-vpu-blk-ctrl", @@ -599,6 +715,9 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = { }, { .compatible = "fsl,imx8mn-disp-blk-ctrl", .data = &imx8mn_disp_blk_ctl_dev_data + }, { + .compatible = "fsl,imx8mp-media-blk-ctrl", + .data = &imx8mp_media_blk_ctl_dev_data }, { /* Sentinel */ } -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/4] soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl 2022-02-28 15:47 ` [PATCH 2/4] soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl Paul Elder @ 2022-02-28 16:45 ` Laurent Pinchart 0 siblings, 0 replies; 8+ messages in thread From: Laurent Pinchart @ 2022-02-28 16:45 UTC (permalink / raw) To: Paul Elder Cc: Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Lucas Stach, Adam Ford, Dan Carpenter, Philipp Zabel, linux-arm-kernel Hi Paul, Thank you for the patch. On Tue, Mar 01, 2022 at 12:47:59AM +0900, Paul Elder wrote: > Add the description for the i.MX8MP media blk-ctrl. > > Signed-off-by: Paul Elder <paul.elder@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > --- > drivers/soc/imx/imx8m-blk-ctrl.c | 123 ++++++++++++++++++++++++++++++- > 1 file changed, 121 insertions(+), 2 deletions(-) > > diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c > index 511e74f0db8a..a0a0d2d7ca4a 100644 > --- a/drivers/soc/imx/imx8m-blk-ctrl.c > +++ b/drivers/soc/imx/imx8m-blk-ctrl.c > @@ -15,10 +15,11 @@ > > #include <dt-bindings/power/imx8mm-power.h> > #include <dt-bindings/power/imx8mn-power.h> > +#include <dt-bindings/power/imx8mp-power.h> > > #define BLK_SFT_RSTN 0x0 > #define BLK_CLK_EN 0x4 > -#define BLK_MIPI_RESET_DIV 0x8 /* Mini/Nano DISPLAY_BLK_CTRL only */ > +#define BLK_MIPI_RESET_DIV 0x8 /* Mini/Nano/Plus DISPLAY_BLK_CTRL only */ > > struct imx8m_blk_ctrl_domain; > > @@ -40,7 +41,7 @@ struct imx8m_blk_ctrl_domain_data { > u32 clk_mask; > > /* > - * i.MX8M Mini and Nano have a third DISPLAY_BLK_CTRL register > + * i.MX8M Mini, Nano and Plus have a third DISPLAY_BLK_CTRL register > * which is used to control the reset for the MIPI Phy. > * Since it's only present in certain circumstances, > * an if-statement should be used before setting and clearing this > @@ -589,6 +590,121 @@ static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = { > .num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data), > }; > > +static int imx8mp_media_power_notifier(struct notifier_block *nb, > + unsigned long action, void *data) > +{ > + struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, > + power_nb); > + > + if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) > + return NOTIFY_OK; > + > + /* Enable bus clock and deassert bus reset */ > + regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8)); > + regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8)); > + > + /* > + * On power up we have no software backchannel to the GPC to > + * wait for the ADB handshake to happen, so we just delay for a > + * bit. On power down the GPC driver waits for the handshake. > + */ > + if (action == GENPD_NOTIFY_ON) > + udelay(5); > + > + return NOTIFY_OK; > +} > + > +/* > + * From i.MX 8M Plus Applications Processor Reference Manual, Rev. 1, > + * section 13.2.2, 13.2.3 > + * isp-ahb and dwe are not in Figure 13-5. Media BLK_CTRL Clocks > + */ > +static const struct imx8m_blk_ctrl_domain_data imx8mp_media_blk_ctl_domain_data[] = { > + [IMX8MP_MEDIABLK_PD_MIPI_DSI_1] = { > + .name = "mediablk-mipi-dsi-1", > + .clk_names = (const char *[]){ "apb", "phy", }, > + .num_clks = 2, > + .gpc_name = "mipi-dsi1", > + .rst_mask = BIT(0) | BIT(1), > + .clk_mask = BIT(0) | BIT(1), > + .mipi_phy_rst_mask = BIT(17), > + }, > + [IMX8MP_MEDIABLK_PD_MIPI_CSI2_1] = { > + .name = "mediablk-mipi-csi2-1", > + .clk_names = (const char *[]){ "apb", "cam1" }, > + .num_clks = 2, > + .gpc_name = "mipi-csi1", > + .rst_mask = BIT(2) | BIT(3), > + .clk_mask = BIT(2) | BIT(3), > + .mipi_phy_rst_mask = BIT(16), > + }, > + [IMX8MP_MEDIABLK_PD_LCDIF_1] = { > + .name = "mediablk-lcdif-1", > + .clk_names = (const char *[]){ "disp1", "apb", "axi", }, > + .num_clks = 3, > + .gpc_name = "lcdif1", > + .rst_mask = BIT(4) | BIT(5) | BIT(23), > + .clk_mask = BIT(4) | BIT(5) | BIT(23), > + }, > + [IMX8MP_MEDIABLK_PD_ISI] = { > + .name = "mediablk-isi", > + .clk_names = (const char *[]){ "axi", "apb" }, > + .num_clks = 2, > + .gpc_name = "isi", > + .rst_mask = BIT(6) | BIT(7), > + .clk_mask = BIT(6) | BIT(7), > + }, > + [IMX8MP_MEDIABLK_PD_MIPI_CSI2_2] = { > + .name = "mediablk-mipi-csi2-2", > + .clk_names = (const char *[]){ "apb", "cam2" }, > + .num_clks = 2, > + .gpc_name = "mipi-csi2", > + .rst_mask = BIT(9) | BIT(10), > + .clk_mask = BIT(9) | BIT(10), > + .mipi_phy_rst_mask = BIT(30), > + }, > + [IMX8MP_MEDIABLK_PD_LCDIF_2] = { > + .name = "mediablk-lcdif-2", > + .clk_names = (const char *[]){ "disp1", "apb", "axi", }, > + .num_clks = 3, > + .gpc_name = "lcdif2", > + .rst_mask = BIT(11) | BIT(12) | BIT(24), > + .clk_mask = BIT(11) | BIT(12) | BIT(24), > + }, > + [IMX8MP_MEDIABLK_PD_ISP] = { > + .name = "mediablk-isp", > + .clk_names = (const char *[]){ "isp", "axi", "apb" }, > + .num_clks = 3, > + .gpc_name = "isp", > + .rst_mask = BIT(16) | BIT(17) | BIT(18), > + .clk_mask = BIT(16) | BIT(17) | BIT(18), > + }, > + [IMX8MP_MEDIABLK_PD_DWE] = { > + .name = "mediablk-dwe", > + .clk_names = (const char *[]){ "axi", "apb" }, > + .num_clks = 2, > + .gpc_name = "dwe", > + .rst_mask = BIT(19) | BIT(20) | BIT(21), > + .clk_mask = BIT(19) | BIT(20) | BIT(21), > + }, > + [IMX8MP_MEDIABLK_PD_MIPI_DSI_2] = { > + .name = "mediablk-mipi-dsi-2", > + .clk_names = (const char *[]){ "phy", }, > + .num_clks = 1, > + .gpc_name = "mipi-dsi2", > + .rst_mask = BIT(22), > + .clk_mask = BIT(22), > + .mipi_phy_rst_mask = BIT(29), > + }, > +}; > + > +static const struct imx8m_blk_ctrl_data imx8mp_media_blk_ctl_dev_data = { > + .max_reg = 0x138, > + .power_notifier_fn = imx8mp_media_power_notifier, > + .domains = imx8mp_media_blk_ctl_domain_data, > + .num_domains = ARRAY_SIZE(imx8mp_media_blk_ctl_domain_data), > +}; > + > static const struct of_device_id imx8m_blk_ctrl_of_match[] = { > { > .compatible = "fsl,imx8mm-vpu-blk-ctrl", > @@ -599,6 +715,9 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = { > }, { > .compatible = "fsl,imx8mn-disp-blk-ctrl", > .data = &imx8mn_disp_blk_ctl_dev_data > + }, { > + .compatible = "fsl,imx8mp-media-blk-ctrl", > + .data = &imx8mp_media_blk_ctl_dev_data > }, { > /* Sentinel */ > } -- Regards, Laurent Pinchart _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 3/4] arm64: dts: imx8mp: Add MEDIAMIX power domains 2022-02-28 15:47 [PATCH 0/4] imx8mp: Add media block control Paul Elder 2022-02-28 15:47 ` [PATCH 1/4] dt-bindings: soc: Add i.MX8MP media block control DT bindings Paul Elder 2022-02-28 15:47 ` [PATCH 2/4] soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl Paul Elder @ 2022-02-28 15:48 ` Paul Elder 2022-02-28 15:48 ` [PATCH 4/4] arm64: dts: imx8mp: Add MEDIA_BLK_CTRL Paul Elder 3 siblings, 0 replies; 8+ messages in thread From: Paul Elder @ 2022-02-28 15:48 UTC (permalink / raw) To: Rob Herring, Shawn Guo, Sascha Hauer Cc: Laurent Pinchart, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Joakim Zhang, Lucas Stach, Peng Fan, Marek Vasut, Jacky Bai, Daniel Baluta, Zhen Lei, devicetree, linux-arm-kernel From: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Add the power domains related to the MEDIAMIX to the GPC. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index c89acb53be4a..eecd820a1193 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -488,6 +488,11 @@ pgc { #address-cells = <1>; #size-cells = <0>; + pgc_mipi_phy1: power-domain@0 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>; + }; + pgc_pcie_phy: power-domain@1 { #power-domain-cells = <0>; reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>; @@ -530,6 +535,21 @@ pgc_gpu3d: power-domain@9 { power-domains = <&pgc_gpumix>; }; + pgc_mediamix: power-domain@10 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + assigned-clock-rates = <500000000>, <200000000>; + }; + + pgc_mipi_phy2: power-domain@16 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; + }; + pgc_hsiomix: power-domains@17 { #power-domain-cells = <0>; reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; @@ -539,6 +559,12 @@ pgc_hsiomix: power-domains@17 { assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; assigned-clock-rates = <500000000>; }; + + pgc_ispdwp: power-domain@18 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_DIV>; + }; }; }; }; -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 4/4] arm64: dts: imx8mp: Add MEDIA_BLK_CTRL 2022-02-28 15:47 [PATCH 0/4] imx8mp: Add media block control Paul Elder ` (2 preceding siblings ...) 2022-02-28 15:48 ` [PATCH 3/4] arm64: dts: imx8mp: Add MEDIAMIX power domains Paul Elder @ 2022-02-28 15:48 ` Paul Elder 3 siblings, 0 replies; 8+ messages in thread From: Paul Elder @ 2022-02-28 15:48 UTC (permalink / raw) To: Rob Herring, Shawn Guo, Sascha Hauer Cc: Paul Elder, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, Joakim Zhang, Laurent Pinchart, Peng Fan, Lucas Stach, Marek Vasut, Zhen Lei, Daniel Baluta, Jacky Bai, devicetree, linux-arm-kernel Add a DT node for the MEDIA_BLK_CTRL, which provides power domains for the camera and display devices. Signed-off-by: Paul Elder <paul.elder@ideasonboard.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 40 +++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index eecd820a1193..a1fdb96024d0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -984,6 +984,46 @@ eqos: ethernet@30bf0000 { }; }; + aips4: bus@32c00000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x32c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + media_blk_ctrl: blk-ctrl@32ec0000 { + compatible = "fsl,imx8mp-media-blk-ctrl", + "syscon"; + reg = <0x32ec0000 0x10000>; + power-domains = <&pgc_mediamix>, + <&pgc_mipi_phy1>, + <&pgc_mipi_phy1>, + <&pgc_mediamix>, + <&pgc_mediamix>, + <&pgc_mipi_phy2>, + <&pgc_mediamix>, + <&pgc_ispdwp>, + <&pgc_ispdwp>, + <&pgc_mipi_phy2>; + power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", + "lcdif1", "isi", "mipi-csi2", + "lcdif2", "isp", "dwe", + "mipi-dsi2"; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>; + clock-names = "apb", "axi", "cam1", "cam2", + "disp1", "disp2", "isp", "phy"; + + #power-domain-cells = <1>; + }; + }; + gpu3d: gpu@38000000 { compatible = "vivante,gc"; reg = <0x38000000 0x8000>; -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-03-10 19:54 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-02-28 15:47 [PATCH 0/4] imx8mp: Add media block control Paul Elder 2022-02-28 15:47 ` [PATCH 1/4] dt-bindings: soc: Add i.MX8MP media block control DT bindings Paul Elder 2022-02-28 16:41 ` Laurent Pinchart 2022-03-10 19:53 ` Rob Herring 2022-02-28 15:47 ` [PATCH 2/4] soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl Paul Elder 2022-02-28 16:45 ` Laurent Pinchart 2022-02-28 15:48 ` [PATCH 3/4] arm64: dts: imx8mp: Add MEDIAMIX power domains Paul Elder 2022-02-28 15:48 ` [PATCH 4/4] arm64: dts: imx8mp: Add MEDIA_BLK_CTRL Paul Elder
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